MMC aware IO scheduler?

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Has anybody thought about MMC aware IO scheduler?

Such scheduler would try to merge writes on the same eraseblock
even if there were gaps between the writes by reading the gaps
first.  Such merges would also be considered for writes on
separate erase blocks if they are close enough.

You may ask why bother.

I have tested a board with eMMC with 512MiB erase block which can
write 20 MiB/s when writes are contiguous with block size of 512
MiB.  Write time is then 20 ms per erase block at mmc driver from
startting to send the read command to mmc_request_done().

But if the writes are to randomly chosen erase block, write times
jumps to 250 ms and is pretty constant regardless of the write
size from 512 bytes to 512 KiB or offset or alignment.

Reading a random erase block takes 30ms. Read speed is< not constant
but grows slowly from 16KiB @ 11 MiB/s to 2 MiB @ 24 MiB/s. The 
device seems also to like sequential reads.

With these figures the cost of reading a gap between two writes
takes <= 25ms, writing a whole erase block takes 270ms,
altogether about 300ms. Writing two any size writes separately to
the same erase blcok would take 510ms.

The same speedup applies roughly to writing two writes to
consecutive erase blocks with gap between the writes.

Jarkko Lavinen

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