On 09/10/2015 01:23 AM, Christoph Lameter wrote: > On Wed, 9 Sep 2015, Paul E. McKenney wrote: > >> > > > A processor that can randomly defer writes to cachelines in the face of >> > > > other processors owning cachelines exclusively does not seem sane to me. >> > > > In fact its no longer exclusive. >> > > >> > > Welcome to the wonderful world of store buffers, which are present even >> > > on strongly ordered systems such as x86 and the mainframe. >> > >> > Store buffers hold complete cachelines that have been written to by a >> > processor. >> >> In many cases, partial cachelines. If the cacheline is not available >> locally, the processor cannot know the contents of the rest of the cache >> line, only the contents of the portion that it recently stored into. > > For a partial cacheline it would have to read the rest of the cacheline > before updating. And I would expect the processor to have exclusive access > to the cacheline that is held in a store buffer. If not then there is > trouble afoot. IIRC that (or something similar with same guarantees) basically happens on x86 when you use the LOCK prefix, i.e. for atomic inc etc. Doing that always would destroy performance. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@xxxxxxxxx. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"dont@xxxxxxxxx";> email@xxxxxxxxx </a>