2015-08-24 18:44 GMT+03:00 Vladimir Murzin <vladimir.murzin@xxxxxxx>: > > Another option would be having "sparse" shadow memory based on page > extension. I did play with that some time ago based on ideas from > original v1 KASan support for x86/arm - it is how 614be38 "irqchip: > gic-v3: Fix out of bounds access to cpu_logical_map" was caught. > It doesn't require any VA reservations, only some contiguous memory for > the page_ext itself, which serves as indirection level for the 0-order > shadow pages. We won't be able to use inline instrumentation (I could live with that), and most importantly, we won't be able to use stack instrumentation. GCC needs to know shadow address for inline and/or stack instrumentation to generate correct code. > In theory such design can be reused by others 32-bit arches and, I > think, nommu too. Additionally, the shadow pages might be movable with > help of driver-page migration patch series [1]. > The cost is obvious - performance drop, although I didn't bother > measuring it. > > [1] https://lwn.net/Articles/650917/ > > Cheers > Vladimir > -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@xxxxxxxxx. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"dont@xxxxxxxxx";> email@xxxxxxxxx </a>