On Tue, 2015-04-21 at 19:46 -0400, Jerome Glisse wrote: > On Tue, Apr 21, 2015 at 02:44:45PM -0700, Paul E. McKenney wrote: > > Hello! > > > > We have some interest in hardware on devices that is cache-coherent > > with main memory, and in migrating memory between host memory and > > device memory. We believe that we might not be the only ones looking > > ahead to hardware like this, so please see below for a draft of some > > approaches that we have been thinking of. > > > > Thoughts? > > I have posted several time a patchset just for doing that, i am sure > Ben did see it. Search for HMM. I am about to repost it in next couple > weeks. Actually no :-) This is not at all HMM realm. HMM deals with non-cachable (MMIO) device memory that isn't represented by struct page and separate MMUs that allow pages to be selectively unmapped from CPU vs. device. This proposal is about a very different type of device where the device memory is fully cachable from a CPU standpoint, and thus can be represented by struct page, and the device has an MMU that is completely shared with the CPU, ie, the device operates within a given context of the system and if a page is marked read-only or inaccessible, this will be true on both the CPU and the device. Note: IBM is also interested in HMM for devices that don't qualify with the above such as some GPUs or NICs, but this is something *else*. Cheers, Ben. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@xxxxxxxxx. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"dont@xxxxxxxxx";> email@xxxxxxxxx </a>