On 07/20/2014 10:38 PM, Qiaowei Ren wrote:
> +#ifdef CONFIG_X86_INTEL_MPX
> +#define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX)
> +#else
> +#define cpu_has_mpx 0
> +#endif /* CONFIG_X86_INTEL_MPX */
Is this enough checking? Looking at the extension reference, it says:
> 9.3.3
> Enabling of Intel MPX States
> An OS can enable Intel MPX states to support software operation using bounds registers with the following steps:
> • Verify the processor supports XSAVE/XRSTOR/XSETBV/XGETBV instructions and XCR0 by checking
> CPUID.1.ECX.XSAVE[bit 26]=1.
That, I assume the xsave code is already doing.
> • Verify the processor supports both Intel MPX states by checking CPUID.(EAX=0x0D, ECX=0):EAX[4:3] is 11b.
I see these bits _attempting_ to get set in pcntxt_mask via XCNTXT_MASK.
But, I don't see us ever actually checking that they _do_ get set. For
instance, we do this for:
> if ((pcntxt_mask & XSTATE_FPSSE) != XSTATE_FPSSE) {
> pr_err("FP/SSE not shown under xsave features 0x%llx\n",
> pcntxt_mask);
> BUG();
> }
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