On 27-Dec-13, at 2:33 PM, Matthew Wilcox wrote:
Have you considered measuring SHMLBA on different CPU models and
reducing it at boot time? I know that 4MB is the architectural
guarantee
(actually, I seem to remember that 16MB was the architectural
guarantee,
but jsm found some CPU architects who said it would enver exceed 4MB).
I bet some CPUs have considerably lower cache coherency limits.
It's worth looking at. The value is supposed to be returned by the
PDC_CACHE PDC
call but I know my rp3440 returns a value of 0 indicating that the
aliasing boundary
is unknown and may be greater than 16MB.
Dave
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John David Anglin dave.anglin@xxxxxxxx
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