On 12/12/2013 07:55 PM, Mel Gorman wrote:
> There was a large performance regression that was bisected to commit 611ae8e3
> (x86/tlb: enable tlb flush range support for x86). This patch simply changes
> the default balance point between a local and global flush for IvyBridge.
>
> Signed-off-by: Mel Gorman <mgorman@xxxxxxx>
agree to be more conservative.
Reviewed-by: Alex Shi <alex.shi@xxxxxxxxx>
> ---
> arch/x86/kernel/cpu/intel.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> index dc1ec0d..2d93753 100644
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -627,7 +627,7 @@ static void intel_tlb_flushall_shift_set(struct cpuinfo_x86 *c)
> tlb_flushall_shift = 5;
> break;
> case 0x63a: /* Ivybridge */
> - tlb_flushall_shift = 1;
> + tlb_flushall_shift = 2;
> break;
> default:
> tlb_flushall_shift = 6;
>
--
Thanks
Alex
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