On Wed, Dec 04, 2013 at 10:26:13PM +0100, Andi Kleen wrote: > > Let's apply the Intel manual to the earlier example: > > > > CPU 0 CPU 1 CPU 2 > > ----- ----- ----- > > x = 1; r1 = SLA(lock); y = 1; > > SSR(lock, 1); r2 = y; smp_mb(); > > r3 = x; > > > > assert(!(r1 == 1 && r2 == 0 && r3 == 0)); > > Hi Paul, > > We discussed this example with CPU architects and they > agreed that it is valid to rely on (r1 == 1 && r2 == 0 && r3 == 0) > never happening. > > So the MCS code is good without additional barriers. Good to hear!!! Thank you, Andi! Thanx, Paul -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@xxxxxxxxx. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"dont@xxxxxxxxx";> email@xxxxxxxxx </a>