Re: [PATCH v6 4/5] MCS Lock: Barrier corrections

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On Fri, Nov 22, 2013 at 12:06 PM, Paul E. McKenney
<paulmck@xxxxxxxxxxxxxxxxxx> wrote:
>
> I am sorry, but that is not always correct.  For example, in the contended
> case for Tim Chen's MCS queued locks, the x86 acquisition-side handoff
> code does -not- contain any stores or memory-barrier instructions.

So? In order to get *into* that contention code, you will have to go
through the fast-case code. Which will contain a locked instruction.

So I repeat: a "lock" sequence will always be a memory barrier on x86.

                   Linus

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