A few things related to TLB flushing and TLB miss rates I would like to discuss at LSF/MM: 1) A quick update on IPI-less TLB flushing with AMD INVLPGB and Intel RAR, and implications for MM synchronization. Probably no real discussion needed. 2) A discussion on how we might be able to integrate mTHPs into khugepaged, and get TLB miss benefits on AMD and ARM CPUs for processes where full-size THPs cause too much memory waste due to internal fragmentation. Are there any other related topics we should try to fit into the same time slot? -- All Rights Reversed.
