On Thu, 27 Feb 2025 22:38:10 +0000
<shiju.jose@xxxxxxxxxx> wrote:
> From: Shiju Jose <shiju.jose@xxxxxxxxxx>
>
> CXL spec 3.2 section 8.2.10.9.11.2 describes the DDR5 ECS (Error Check
> Scrub) control feature.
> The Error Check Scrub (ECS) is a feature defined in JEDEC DDR5 SDRAM
> Specification (JESD79-5) and allows the DRAM to internally read, correct
> single-bit errors, and write back corrected data bits to the DRAM array
> while providing transparency to error counts.
>
> The ECS control allows the requester to change the log entry type, the ECS
> threshold count (provided the request falls within the limits specified in
> DDR5 mode registers), switch between codeword mode and row count mode, and
> reset the ECS counter.
>
> Register with EDAC device driver, which retrieves the ECS attribute
> descriptors from the EDAC ECS and exposes the ECS control attributes to
> userspace via sysfs. For example, the ECS control for the memory media FRU0
> in CXL mem0 device is located at /sys/bus/edac/devices/cxl_mem0/ecs_fru0/
>
> Signed-off-by: Shiju Jose <shiju.jose@xxxxxxxxxx>
Hmm. No idea why I didn't tag this before. It's been fine for ages.
One really small thing if respinning for some other reason,
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
> +static int cxl_mem_ecs_set_attrs(struct device *dev,
> + struct cxl_ecs_context *cxl_ecs_ctx,
> + int fru_id, struct cxl_ecs_params *params,
> + u8 param_type)
> +{
...
> +
> + /*
> + * Fill attribute to be set for the media FRU
Trivial but could be a single line comment.
> + */
> + ecs_config = le16_to_cpu(fru_rd_attrs[fru_id].ecs_config);
> + switch (param_type) {
> + case CXL_ECS_PARAM_LOG_ENTRY_TYPE:
