On Tue, Feb 25, 2025 at 10:00:38PM -0500, Rik van Riel wrote:
> Add helper functions and definitions needed to use broadcast TLB
> invalidation on AMD EPYC 3 and newer CPUs.
>
> All the functions defined in invlpgb.h are used later in the series.
>
> Compile time disabling X86_FEATURE_INVLPGB when the config
> option is not set allows the compiler to omit unnecessary code.
>
> Signed-off-by: Rik van Riel <riel@xxxxxxxxxxx>
> Tested-by: Manali Shukla <Manali.Shukla@xxxxxxx>
> Tested-by: Brendan Jackman <jackmanb@xxxxxxxxxx>
> Tested-by: Michael Kelley <mhklinux@xxxxxxxxxxx>
> Acked-by: Dave Hansen <dave.hansen@xxxxxxxxx>
> ---
> arch/x86/include/asm/disabled-features.h | 8 +-
> arch/x86/include/asm/tlb.h | 98 ++++++++++++++++++++++++
> 2 files changed, 105 insertions(+), 1 deletion(-)
My edits ontop.
x86/cpu has dropped {disabled,required}-features.h in favor of a new, better
mechanism to compile-time disable X86 features, see below.
--- /tmp/current.patch 2025-02-28 20:44:40.765404608 +0100
+++ /tmp/0001-x86-mm-Add-INVLPGB-support-code.patch 2025-02-28 20:44:18.492326903 +0100
@@ -1,55 +1,38 @@
+From ce22946ea806ae459b4d88767a59b010e70682d5 Mon Sep 17 00:00:00 2001
From: Rik van Riel <riel@xxxxxxxxxxx>
-Date: Tue, 25 Feb 2025 22:00:38 -0500
-Subject: x86/mm: Add INVLPGB support code
+Date: Fri, 28 Feb 2025 20:32:30 +0100
+Subject: [PATCH] x86/mm: Add INVLPGB support code
Add helper functions and definitions needed to use broadcast TLB
-invalidation on AMD EPYC 3 and newer CPUs.
+invalidation on AMD CPUs.
-All the functions defined in invlpgb.h are used later in the series.
-
-Compile time disabling X86_FEATURE_INVLPGB when the config
-option is not set allows the compiler to omit unnecessary code.
+ [ bp:
+ - Cleanup commit message
+ - port it to new Kconfig.cpufeatures machinery
+ - add a comment about flushing any PCID and ASID ]
Signed-off-by: Rik van Riel <riel@xxxxxxxxxxx>
Signed-off-by: Borislav Petkov (AMD) <bp@xxxxxxxxx>
-Acked-by: Dave Hansen <dave.hansen@xxxxxxxxx>
-Tested-by: Manali Shukla <Manali.Shukla@xxxxxxx>
-Tested-by: Brendan Jackman <jackmanb@xxxxxxxxxx>
-Tested-by: Michael Kelley <mhklinux@xxxxxxxxxxx>
Link: https://lore.kernel.org/r/20250226030129.530345-4-riel@xxxxxxxxxxx
---
- arch/x86/include/asm/disabled-features.h | 8 +-
- arch/x86/include/asm/tlb.h | 98 ++++++++++++++++++++++++
- 2 files changed, 105 insertions(+), 1 deletion(-)
-
-diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h
-index c492bdc97b05..625a89259968 100644
---- a/arch/x86/include/asm/disabled-features.h
-+++ b/arch/x86/include/asm/disabled-features.h
-@@ -129,6 +129,12 @@
- #define DISABLE_SEV_SNP (1 << (X86_FEATURE_SEV_SNP & 31))
- #endif
-
-+#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH
-+#define DISABLE_INVLPGB 0
-+#else
-+#define DISABLE_INVLPGB (1 << (X86_FEATURE_INVLPGB & 31))
-+#endif
-+
- /*
- * Make sure to add features to the correct mask
- */
-@@ -146,7 +152,7 @@
- #define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET| \
- DISABLE_CALL_DEPTH_TRACKING|DISABLE_USER_SHSTK)
- #define DISABLED_MASK12 (DISABLE_FRED|DISABLE_LAM)
--#define DISABLED_MASK13 0
-+#define DISABLED_MASK13 (DISABLE_INVLPGB)
- #define DISABLED_MASK14 0
- #define DISABLED_MASK15 0
- #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP| \
+ arch/x86/Kconfig.cpufeatures | 4 ++
+ arch/x86/include/asm/tlb.h | 101 +++++++++++++++++++++++++++++++++++
+ 2 files changed, 105 insertions(+)
+
+diff --git a/arch/x86/Kconfig.cpufeatures b/arch/x86/Kconfig.cpufeatures
+index 5dcc49d928c5..f9af51205f07 100644
+--- a/arch/x86/Kconfig.cpufeatures
++++ b/arch/x86/Kconfig.cpufeatures
+@@ -195,3 +195,7 @@ config X86_DISABLED_FEATURE_FRED
+ config X86_DISABLED_FEATURE_SEV_SNP
+ def_bool y
+ depends on !KVM_AMD_SEV
++
++config X86_DISABLED_FEATURE_BROADCAST_TLB_FLUSH
++ def_bool y
++ depends on !X86_BROADCAST_TLB_FLUSH
diff --git a/arch/x86/include/asm/tlb.h b/arch/x86/include/asm/tlb.h
-index 77f52bc1578a..91c9a4da3ace 100644
+index 77f52bc1578a..45d9c7687d61 100644
--- a/arch/x86/include/asm/tlb.h
+++ b/arch/x86/include/asm/tlb.h
@@ -6,6 +6,9 @@
@@ -62,7 +45,7 @@ index 77f52bc1578a..91c9a4da3ace 100644
static inline void tlb_flush(struct mmu_gather *tlb)
{
-@@ -25,4 +28,99 @@ static inline void invlpg(unsigned long addr)
+@@ -25,4 +28,102 @@ static inline void invlpg(unsigned long addr)
asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
}
@@ -157,11 +140,14 @@ index 77f52bc1578a..91c9a4da3ace 100644
+/* Flush all mappings for all PCIDs except globals. */
+static inline void invlpgb_flush_all_nonglobals(void)
+{
++ /*
++ * @addr=0 means both rax[1] (valid PCID) and rax[2] (valid ASID) are clear
++ * so flush *any* PCID and ASID.
++ */
+ __invlpgb(0, 0, 0, 1, 0, 0);
+ __tlbsync();
+}
-+
#endif /* _ASM_X86_TLB_H */
--
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
