On Mon, 2025-02-24 at 14:27 +0100, Borislav Petkov wrote:
> On Sun, Feb 23, 2025 at 02:48:56PM -0500, Rik van Riel wrote:
> >
> > +++ b/arch/x86/mm/tlb.c
> > @@ -1326,7 +1326,9 @@ void arch_tlbbatch_flush(struct
> > arch_tlbflush_unmap_batch *batch)
> > * a local TLB flush is needed. Optimize this use-case by
> > calling
> > * flush_tlb_func_local() directly in this case.
> > */
> > - if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) {
> > + if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) {
> > + invlpgb_flush_all_nonglobals();
>
> I'm confused. The docs say rAX needs to be 0x6 to do "Invalidate all
> TLB
> entries that match {ASID, PCID} excluding Global". But you're calling
> INVLPGB
> with rAX==0 and the APM doesn't say what this does.
>
> I'm guessing you want this to mean invalidate all non-globals for any
> ASID and
> PCID. So I muss be missing the place in the docs where it says so...
You are right that it does not explicitly say it.
However, it does strongly hint at it:
"The TLB control field is specified in rAX[5:0]. It determines
which components of the address (VA, PCID, ASID) are valid for
comparison in the TLB and whether to include global entries in
the invalidation process.
...
rAX[3:0] provides for various types of invalidations. A few
examples are listed in the following table, but all values
are legal."
This text, to me, suggests we can filter the TLB
invalidations by some combination of virtual address,
PCID, or ASID, or not filter by any of those keys,
and invalidate them all.
Who do we need to ask to confirm that reading?
--
All Rights Reversed.
