On Sun, Jan 19, 2025 at 09:40:13PM -0500, Rik van Riel wrote:
> +/*
> + * INVLPGB does broadcast TLB invalidation across all the CPUs in the system.
> + *
> + * The INVLPGB instruction is weakly ordered, and a batch of invalidations can
> + * be done in a parallel fashion.
> + *
> + * TLBSYNC is used to ensure that pending INVLPGB invalidations initiated from
> + * this CPU have completed.
> + */
> +static inline void __invlpgb(unsigned long asid, unsigned long pcid,
> + unsigned long addr, u16 extra_count,
> + bool pmd_stride, unsigned long flags)
> +{
> + u32 edx = (pcid << 16) | asid;
> + u32 ecx = (pmd_stride << 31) | extra_count;
> + u64 rax = addr | flags;
> +
> + /* INVLPGB; supported in binutils >= 2.36. */
> + asm volatile(".byte 0x0f, 0x01, 0xfe" : : "a" (rax), "c" (ecx), "d" (edx));
> +}
So asid is always 0 (for now), but I'd feel better if that was a u16
argument, less chance funnies when someone starts using it.
We should probably mask or WARN on addr having low bits set, and flags
should then be a u8 or something.
