tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: 77a903cd8e5a91d120ee014c8f8eae74d6c5d0f6 commit: d0a3ac549f389c1511a4df0d7638536305205d20 ubsan: enable for all*config builds date: 4 years, 1 month ago config: powerpc64-randconfig-002-20231105 (https://download.01.org/0day-ci/archive/20250111/202501111602.dSoRi3D5-lkp@xxxxxxxxx/config) compiler: powerpc64-linux-gcc (GCC) 12.4.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250111/202501111602.dSoRi3D5-lkp@xxxxxxxxx/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@xxxxxxxxx> | Closes: https://lore.kernel.org/oe-kbuild-all/202501111602.dSoRi3D5-lkp@xxxxxxxxx/ All warnings (new ones prefixed by >>): drivers/clk/clk-cdce925.c: In function 'cdce925_probe': >> drivers/clk/clk-cdce925.c:717:41: warning: '%d' directive writing between 1 and 11 bytes into a region of size 3 [-Wformat-overflow=] 717 | sprintf(child_name, "PLL%d", i+1); | ^~ drivers/clk/clk-cdce925.c:717:37: note: directive argument in the range [-2147483641, 2147483647] 717 | sprintf(child_name, "PLL%d", i+1); | ^~~~~~~ drivers/clk/clk-cdce925.c:717:17: note: 'sprintf' output between 5 and 15 bytes into a destination of size 6 717 | sprintf(child_name, "PLL%d", i+1); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- drivers/net/ethernet/broadcom/bnx2.c: In function 'bnx2_setup_int_mode': >> drivers/net/ethernet/broadcom/bnx2.c:6303:56: warning: '%d' directive output may be truncated writing between 1 and 10 bytes into a region of size between 2 and 17 [-Wformat-truncation=] 6303 | snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i); | ^~ In function 'bnx2_enable_msix', inlined from 'bnx2_setup_int_mode' at drivers/net/ethernet/broadcom/bnx2.c:6329:3: drivers/net/ethernet/broadcom/bnx2.c:6303:52: note: directive argument in the range [0, 2147483646] 6303 | snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i); | ^~~~~~~ drivers/net/ethernet/broadcom/bnx2.c:6303:17: note: 'snprintf' output between 3 and 27 bytes into a destination of size 18 6303 | snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- drivers/usb/dwc2/gadget.c: In function 'dwc2_hsotg_initep': >> drivers/usb/dwc2/gadget.c:4702:55: warning: '%d' directive output may be truncated writing between 1 and 11 bytes into a region of size 8 [-Wformat-truncation=] 4702 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | ^~ drivers/usb/dwc2/gadget.c:4702:52: note: directive argument in the range [-2147483645, 255] 4702 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | ^~~~~~~~ drivers/usb/dwc2/gadget.c:4702:9: note: 'snprintf' output between 6 and 17 bytes into a destination of size 10 4702 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ vim +717 drivers/clk/clk-cdce925.c 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 636 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 637 static int cdce925_probe(struct i2c_client *client, 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 638 const struct i2c_device_id *id) 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 639 { 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 640 struct clk_cdce925_chip *data; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 641 struct device_node *node = client->dev.of_node; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 642 const char *parent_name; 5508124cccb8bd Akinobu Mita 2017-01-01 643 const char *pll_clk_name[MAX_NUMBER_OF_PLLS] = {NULL,}; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 644 struct clk_init_data init; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 645 u32 value; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 646 int i; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 647 int err; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 648 struct device_node *np_output; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 649 char child_name[6]; 5508124cccb8bd Akinobu Mita 2017-01-01 650 struct regmap_config config = { 5508124cccb8bd Akinobu Mita 2017-01-01 651 .name = "configuration0", 5508124cccb8bd Akinobu Mita 2017-01-01 652 .reg_bits = 8, 5508124cccb8bd Akinobu Mita 2017-01-01 653 .val_bits = 8, 5508124cccb8bd Akinobu Mita 2017-01-01 654 .cache_type = REGCACHE_RBTREE, 5508124cccb8bd Akinobu Mita 2017-01-01 655 }; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 656 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 657 dev_dbg(&client->dev, "%s\n", __func__); d69d0b4384ba80 Phil Reid 2019-06-28 658 d69d0b4384ba80 Phil Reid 2019-06-28 659 err = cdce925_regulator_enable(&client->dev, "vdd"); d69d0b4384ba80 Phil Reid 2019-06-28 660 if (err) d69d0b4384ba80 Phil Reid 2019-06-28 661 return err; d69d0b4384ba80 Phil Reid 2019-06-28 662 d69d0b4384ba80 Phil Reid 2019-06-28 663 err = cdce925_regulator_enable(&client->dev, "vddout"); d69d0b4384ba80 Phil Reid 2019-06-28 664 if (err) d69d0b4384ba80 Phil Reid 2019-06-28 665 return err; d69d0b4384ba80 Phil Reid 2019-06-28 666 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 667 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 668 if (!data) 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 669 return -ENOMEM; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 670 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 671 data->i2c_client = client; 5508124cccb8bd Akinobu Mita 2017-01-01 672 data->chip_info = &clk_cdce925_chip_info_tbl[id->driver_data]; 5508124cccb8bd Akinobu Mita 2017-01-01 673 config.max_register = CDCE925_OFFSET_PLL + 5508124cccb8bd Akinobu Mita 2017-01-01 674 data->chip_info->num_plls * 0x10 - 1; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 675 data->regmap = devm_regmap_init(&client->dev, ®map_cdce925_bus, 5508124cccb8bd Akinobu Mita 2017-01-01 676 &client->dev, &config); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 677 if (IS_ERR(data->regmap)) { 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 678 dev_err(&client->dev, "failed to allocate register map\n"); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 679 return PTR_ERR(data->regmap); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 680 } 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 681 i2c_set_clientdata(client, data); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 682 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 683 parent_name = of_clk_get_parent_name(node, 0); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 684 if (!parent_name) { 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 685 dev_err(&client->dev, "missing parent clock\n"); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 686 return -ENODEV; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 687 } 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 688 dev_dbg(&client->dev, "parent is: %s\n", parent_name); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 689 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 690 if (of_property_read_u32(node, "xtal-load-pf", &value) == 0) 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 691 regmap_write(data->regmap, 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 692 CDCE925_REG_XCSEL, (value << 3) & 0xF8); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 693 /* PWDN bit */ 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 694 regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 695 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 696 /* Set input source for Y1 to be the XTAL */ 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 697 regmap_update_bits(data->regmap, 0x02, BIT(7), 0); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 698 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 699 init.ops = &cdce925_pll_ops; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 700 init.flags = 0; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 701 init.parent_names = &parent_name; 9416a5f8842a37 Colin Ian King 2017-09-05 702 init.num_parents = 1; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 703 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 704 /* Register PLL clocks */ 5508124cccb8bd Akinobu Mita 2017-01-01 705 for (i = 0; i < data->chip_info->num_plls; ++i) { e665f029a283af Rob Herring 2018-08-28 706 pll_clk_name[i] = kasprintf(GFP_KERNEL, "%pOFn.pll%d", e665f029a283af Rob Herring 2018-08-28 707 client->dev.of_node, i); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 708 init.name = pll_clk_name[i]; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 709 data->pll[i].chip = data; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 710 data->pll[i].hw.init = &init; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 711 data->pll[i].index = i; a85d11712dd13f Stephen Boyd 2016-06-01 712 err = devm_clk_hw_register(&client->dev, &data->pll[i].hw); a85d11712dd13f Stephen Boyd 2016-06-01 713 if (err) { 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 714 dev_err(&client->dev, "Failed register PLL %d\n", i); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 715 goto error; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 716 } 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 @717 sprintf(child_name, "PLL%d", i+1); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 718 np_output = of_get_child_by_name(node, child_name); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 719 if (!np_output) 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 720 continue; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 721 if (!of_property_read_u32(np_output, 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 722 "clock-frequency", &value)) { a85d11712dd13f Stephen Boyd 2016-06-01 723 err = clk_set_rate(data->pll[i].hw.clk, value); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 724 if (err) 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 725 dev_err(&client->dev, 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 726 "unable to set PLL frequency %ud\n", 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 727 value); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 728 } 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 729 if (!of_property_read_u32(np_output, 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 730 "spread-spectrum", &value)) { 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 731 u8 flag = of_property_read_bool(np_output, 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 732 "spread-spectrum-center") ? 0x80 : 0x00; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 733 regmap_update_bits(data->regmap, 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 734 0x16 + (i*CDCE925_OFFSET_PLL), 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 735 0x80, flag); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 736 regmap_update_bits(data->regmap, 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 737 0x12 + (i*CDCE925_OFFSET_PLL), 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 738 0x07, value & 0x07); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 739 } 0b85de7cef013e Alexey Khoroshilov 2018-08-22 740 of_node_put(np_output); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 741 } 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 742 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 743 /* Register output clock Y1 */ 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 744 init.ops = &cdce925_clk_y1_ops; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 745 init.flags = 0; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 746 init.num_parents = 1; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 747 init.parent_names = &parent_name; /* Mux Y1 to input */ e665f029a283af Rob Herring 2018-08-28 748 init.name = kasprintf(GFP_KERNEL, "%pOFn.Y1", client->dev.of_node); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 749 data->clk[0].chip = data; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 750 data->clk[0].hw.init = &init; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 751 data->clk[0].index = 0; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 752 data->clk[0].pdiv = 1; a85d11712dd13f Stephen Boyd 2016-06-01 753 err = devm_clk_hw_register(&client->dev, &data->clk[0].hw); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 754 kfree(init.name); /* clock framework made a copy of the name */ a85d11712dd13f Stephen Boyd 2016-06-01 755 if (err) { 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 756 dev_err(&client->dev, "clock registration Y1 failed\n"); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 757 goto error; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 758 } 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 759 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 760 /* Register output clocks Y2 .. Y5*/ 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 761 init.ops = &cdce925_clk_ops; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 762 init.flags = CLK_SET_RATE_PARENT; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 763 init.num_parents = 1; 5508124cccb8bd Akinobu Mita 2017-01-01 764 for (i = 1; i < data->chip_info->num_outputs; ++i) { e665f029a283af Rob Herring 2018-08-28 765 init.name = kasprintf(GFP_KERNEL, "%pOFn.Y%d", e665f029a283af Rob Herring 2018-08-28 766 client->dev.of_node, i+1); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 767 data->clk[i].chip = data; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 768 data->clk[i].hw.init = &init; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 769 data->clk[i].index = i; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 770 data->clk[i].pdiv = 1; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 771 switch (i) { 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 772 case 1: 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 773 case 2: 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 774 /* Mux Y2/3 to PLL1 */ 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 775 init.parent_names = &pll_clk_name[0]; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 776 break; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 777 case 3: 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 778 case 4: 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 779 /* Mux Y4/5 to PLL2 */ 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 780 init.parent_names = &pll_clk_name[1]; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 781 break; 5508124cccb8bd Akinobu Mita 2017-01-01 782 case 5: 5508124cccb8bd Akinobu Mita 2017-01-01 783 case 6: 5508124cccb8bd Akinobu Mita 2017-01-01 784 /* Mux Y6/7 to PLL3 */ 5508124cccb8bd Akinobu Mita 2017-01-01 785 init.parent_names = &pll_clk_name[2]; 5508124cccb8bd Akinobu Mita 2017-01-01 786 break; 5508124cccb8bd Akinobu Mita 2017-01-01 787 case 7: 5508124cccb8bd Akinobu Mita 2017-01-01 788 case 8: 5508124cccb8bd Akinobu Mita 2017-01-01 789 /* Mux Y8/9 to PLL4 */ 5508124cccb8bd Akinobu Mita 2017-01-01 790 init.parent_names = &pll_clk_name[3]; 5508124cccb8bd Akinobu Mita 2017-01-01 791 break; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 792 } a85d11712dd13f Stephen Boyd 2016-06-01 793 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 794 kfree(init.name); /* clock framework made a copy of the name */ a85d11712dd13f Stephen Boyd 2016-06-01 795 if (err) { 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 796 dev_err(&client->dev, "clock registration failed\n"); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 797 goto error; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 798 } 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 799 } 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 800 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 801 /* Register the output clocks */ a85d11712dd13f Stephen Boyd 2016-06-01 802 err = of_clk_add_hw_provider(client->dev.of_node, of_clk_cdce925_get, a85d11712dd13f Stephen Boyd 2016-06-01 803 data); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 804 if (err) 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 805 dev_err(&client->dev, "unable to add OF clock provider\n"); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 806 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 807 err = 0; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 808 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 809 error: 5508124cccb8bd Akinobu Mita 2017-01-01 810 for (i = 0; i < data->chip_info->num_plls; ++i) 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 811 /* clock framework made a copy of the name */ 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 812 kfree(pll_clk_name[i]); 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 813 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 814 return err; 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 815 } 19fbbbbcd3a3a8 Mike Looijmans 2015-06-03 816 :::::: The code at line 717 was first introduced by commit :::::: 19fbbbbcd3a3a8e307a4768784166abf7b55b779 Add TI CDCE925 I2C controlled clock synthesizer driver :::::: TO: Mike Looijmans <mike.looijmans@xxxxxxxx> :::::: CC: Michael Turquette <mturquette@xxxxxxxxxx> -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki
