> On 30 Dec 2024, at 19:53, Rik van Riel <riel@xxxxxxxxxxx> wrote:
>
> --- a/arch/x86/kernel/cpu/amd.c
> +++ b/arch/x86/kernel/cpu/amd.c
> @@ -1143,6 +1143,14 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
>
> /* Max number of pages INVLPGB can invalidate in one shot */
> invlpgb_count_max = (edx & 0xffff) + 1;
> +
> + /* If supported, enable translation cache extensions (TCE) */
> + cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
> + if (ecx & BIT(17)) {
> + u64 msr = native_read_msr(MSR_EFER);;
> + msr |= BIT(15);
> + wrmsrl(MSR_EFER, msr);
> + }
> }
Sorry for the gradual/delayed feedback.
Is it possible to avoid the BIT(x) and just add the bits to
arch/x86/include/asm/msr-index.h like EFER_FFXSR ?
