[PATCH 10/11] x86/mm: enable AMD translation cache extensions

[Rik van Riel <riel@xxxxxxxxxxx>]

With AMD TCE (translation cache extensions) only the intermediate mappings
that cover the address range zapped by INVLPG / INVLPGB get invalidated,
rather than all intermediate mappings getting zapped at every TLB invalidation.

This can help reduce the TLB miss rate, by keeping more intermediate
mappings in the cache.