On Mon, Dec 16, 2024 at 01:22:05PM +0100, Oleg Nesterov wrote: > OK, thanks, I am starting to share your concerns... > > Oleg. > > On 12/16, David Laight wrote: > > > > From: Oleg Nesterov > > > Sent: 16 December 2024 10:13 > > > > > > David, > > > > > > let me say first that my understanding of this magic is very limited, > > > please correct me. > > > > I only (half) understand what the 'magic' has to accomplish and > > some of the pitfalls. > > > > I've copied linux-mm - someone there might know more. > > > > > On 12/16, David Laight wrote: > > > > > > > > It all depends on how hard __replace_page() tries to be atomic. > > > > The page has to change from one backed by the executable to a private > > > > one backed by swap - otherwise you can't write to it. > > > > > > This is what uprobe_write_opcode() does, > > > > And will be enough for single byte changes - they'll be picked up > > at some point after the change. > > > > > > But the problems arise when the instruction prefetch unit has read > > > > part of the 5-byte instruction (it might even only read half a cache > > > > line at a time). > > > > I'm not sure how long the pipeline can sit in that state - but I > > > > can do a memory read of a PCIe address that takes ~3000 clocks. > > > > (And a misaligned AVX-512 read is probably eight 8-byte transfers.) > > > > > > > > So I think you need to force an interrupt while the PTE is invalid. > > > > And that need to be simultaneous on all cpu running that process. > > > > > > __replace_page() does ptep_get_and_clear(old_pte) + flush_tlb_page(). > > > > > > That's not enough? > > > > I doubt it. As I understand it. > > The hardware page tables will be shared by all the threads of a process. > > So unless you hard synchronise all the cpu (and flush the TLB) while the > > PTE is being changed there is always the possibility of a cpu picking up > > the new PTE before the IPI that (I presume) flush_tlb_page() generates > > is processed. > > If that happens when the instruction you are patching is part-read into > > the instruction decode buffer then you'll execute a mismatch of the two > > instructions. if 5 byte update would be a problem, I guess we could workaround that through partial updates using int3 like we do in text_poke_bp_batch? - changing nop5 instruction to 'call xxx' - write int3 to first byte of nop5 instruction - have poke_int3_handler to emulate nop5 if int3 is triggered - write rest of the call instruction to nop5 last 4 bytes - overwrite first byte of nop5 with call opcode similar update from 'call xxx' -> 'nop5' thanks, jirka > > > > I can't remember the outcome of discussions about live-patching kernel > > code - and I'm sure that was aligned 32bit writes. > > > > > > > > > Stopping the process using ptrace would do it. > > > > > > Not an option :/ > > > > Thought you'd say that. > > > > David > > > > > > > > Oleg. > > > > - > > Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK > > Registration No: 1397386 (Wales) > > >
