On 5 Dec 2024, at 5:37, Xu Lu wrote: > This patch series attempts to break through the limitation of MMU and > supports larger base page on RISC-V, which only supports 4K page size > now. The key idea is to always manage and allocate memory at a > granularity of 64K and use SVNAPOT to accelerate address translation. > This is the second version and the detailed introduction can be found > in [1]. > > Changes from v1: > - Rebase on v6.12. > > - Adjust the page table entry shift to reduce page table memory usage. > For example, in SV39, the traditional va behaves as: > > ---------------------------------------------- > | pgd index | pmd index | pte index | offset | > ---------------------------------------------- > | 38 30 | 29 21 | 20 12 | 11 0 | > ---------------------------------------------- > > When we choose 64K as basic software page, va now behaves as: > > ---------------------------------------------- > | pgd index | pmd index | pte index | offset | > ---------------------------------------------- > | 38 34 | 33 25 | 24 16 | 15 0 | > ---------------------------------------------- > > - Fix some bugs in v1. > > Thanks in advance for comments. > > [1] https://lwn.net/Articles/952722/ This looks very interesting. Can you cc me and linux-mm@xxxxxxxxx in the future? Thanks. Have you thought about doing it for ARM64 4KB as well? ARM64’s contig PTE should have similar effect of RISC-V’s SVNAPOT, right? > > Xu Lu (21): > riscv: mm: Distinguish hardware base page and software base page > riscv: mm: Configure satp with hw page pfn > riscv: mm: Reimplement page table entry structures > riscv: mm: Reimplement page table entry constructor function > riscv: mm: Reimplement conversion functions between page table entry > riscv: mm: Avoid pte constructor during pte conversion > riscv: mm: Reimplement page table entry get function > riscv: mm: Reimplement page table entry atomic get function > riscv: mm: Replace READ_ONCE with atomic pte get function > riscv: mm: Reimplement PTE A/D bit check function > riscv: mm: Reimplement mk_huge_pte function > riscv: mm: Reimplement tlb flush function > riscv: mm: Adjust PGDIR/P4D/PUD/PMD_SHIFT > riscv: mm: Only apply svnapot region bigger than software page > riscv: mm: Adjust FIX_BTMAPS_SLOTS for variable PAGE_SIZE > riscv: mm: Adjust FIX_FDT_SIZE for variable PMD_SIZE > riscv: mm: Apply Svnapot for base page mapping if possible > riscv: Kconfig: Introduce 64K page size > riscv: Kconfig: Adjust mmap rnd bits for 64K Page > riscv: mm: Adjust address space layout and init page table for 64K > Page > riscv: mm: Update EXEC_PAGESIZE for 64K Page > > arch/riscv/Kconfig | 34 +- > arch/riscv/include/asm/fixmap.h | 3 +- > arch/riscv/include/asm/hugetlb.h | 5 + > arch/riscv/include/asm/page.h | 56 ++- > arch/riscv/include/asm/pgtable-32.h | 12 +- > arch/riscv/include/asm/pgtable-64.h | 128 ++++-- > arch/riscv/include/asm/pgtable-bits.h | 3 +- > arch/riscv/include/asm/pgtable.h | 564 +++++++++++++++++++++++--- > arch/riscv/include/asm/tlbflush.h | 26 +- > arch/riscv/include/uapi/asm/param.h | 24 ++ > arch/riscv/kernel/head.S | 4 +- > arch/riscv/kernel/hibernate.c | 21 +- > arch/riscv/mm/context.c | 7 +- > arch/riscv/mm/fault.c | 15 +- > arch/riscv/mm/hugetlbpage.c | 30 +- > arch/riscv/mm/init.c | 45 +- > arch/riscv/mm/kasan_init.c | 7 +- > arch/riscv/mm/pgtable.c | 111 ++++- > arch/riscv/mm/tlbflush.c | 31 +- > arch/s390/include/asm/hugetlb.h | 2 +- > include/asm-generic/hugetlb.h | 5 +- > include/linux/pgtable.h | 21 + > kernel/events/core.c | 6 +- > mm/debug_vm_pgtable.c | 6 +- > mm/gup.c | 10 +- > mm/hmm.c | 2 +- > mm/hugetlb.c | 4 +- > mm/mapping_dirty_helpers.c | 2 +- > mm/memory.c | 4 +- > mm/mprotect.c | 2 +- > mm/ptdump.c | 8 +- > mm/sparse-vmemmap.c | 2 +- > mm/vmscan.c | 2 +- > 33 files changed, 1029 insertions(+), 173 deletions(-) > create mode 100644 arch/riscv/include/uapi/asm/param.h > > -- > 2.20.1 Best Regards, Yan, Zi
