On Mon, Nov 04, 2024 at 10:10:48AM +0100, Christoph Hellwig wrote: > >> + arch_sync_dma_for_device(phys, size, dir); > > > > Plus if the aim is to pass P2P and whatever arbitrary physical addresses > > through here as well, how can we be sure this isn't going to explode? > > That's a good point. Only mapped through host bridge P2P can even > end up here, so the address is a perfectly valid physical address > in the host. But I'm not sure if all arch_sync_dma_for_device > implementations handle IOMMU memory fine. I was told on x86 if you do a cache flush operation on MMIO there is a chance it will MCE. Recently had some similar discussions about ARM where it was asserted some platforms may have similar. It would be safest to only call arch flushing calls on memory that is mapped cachable. We can assume that a P2P target is never CPU mapped cachable, regardless of how the DMA is routed. Jason
