On Mon, Sep 09, 2024 at 04:03:55AM +0000, Ankit Agrawal wrote: > > More architectures / More page sizes > > ------------------------------------ > > > > Currently only x86_64 (2M+1G) and arm64 (2M) are supported. There seems to > > have plan to support arm64 1G later on top of this series [2]. > > > > Any arch will need to first support THP / THP_1G, then provide a special > > bit in pmds/puds to support huge pfnmaps. > > Just to confirm, would this also not support 512M for 64K pages on aarch64 > with special PMD? Or am I missing something? I don't think it's properly tested yet, but logically it should be supported indeed, as here what matters is "pmd/pud", not the explicit size that it uses. > > > remap_pfn_range() support > > ------------------------- > > > > Currently, remap_pfn_range() still only maps PTEs. With the new option, > > remap_pfn_range() can logically start to inject either PMDs or PUDs when > > the alignment requirements match on the VAs. > > > > When the support is there, it should be able to silently benefit all > > drivers that is using remap_pfn_range() in its mmap() handler on better TLB > > hit rate and overall faster MMIO accesses similar to processor on hugepages. > > Does Peter or other folks know of an ongoing effort/patches to extend > remap_pfn_range() to use this? Not away of any from my side. Thanks, -- Peter Xu
