tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master head: 9aaeb87ce1e966169a57f53a02ba05b30880ffb8 commit: be28b79807f6ed29ff87ffedfac848ea50c1e2fe [10291/10296] fix up for "lib/string_choices: Add str_true_false()/str_false_true() helper' config: s390-randconfig-r004-20220823 (https://download.01.org/0day-ci/archive/20240908/202409080140.ncu18wOy-lkp@xxxxxxxxx/config) compiler: s390-linux-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240908/202409080140.ncu18wOy-lkp@xxxxxxxxx/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@xxxxxxxxx> | Closes: https://lore.kernel.org/oe-kbuild-all/202409080140.ncu18wOy-lkp@xxxxxxxxx/ All warnings (new ones prefixed by >>): drivers/gpu/drm/amd/amdgpu/mes_v11_0.c: In function 'mes_v11_0_reset_queue_mmio': >> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c:416:18: warning: this 'if' clause does not guard... [-Wmisleading-indentation] 416 | for (i = 0; i < adev->usec_timeout; i++) { | ^~ In file included from include/linux/delay.h:27, from drivers/gpu/drm/amd/amdgpu/../display/dc/os_types.h:32, from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:29, from drivers/gpu/drm/amd/amdgpu/../include/dm_pp_interface.h:26, from drivers/gpu/drm/amd/amdgpu/amdgpu.h:62, from drivers/gpu/drm/amd/amdgpu/mes_v11_0.c:26: arch/s390/include/asm/delay.h:21:19: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the 'if' 21 | #define udelay(n) __udelay((unsigned long)(n)) | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/mes_v11_0.c:418:25: note: in expansion of macro 'udelay' 418 | break; | ^~~~~~ vim +/if +416 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c 028c3fb37e705b Jack Xiao 2022-04-13 363 178ad0e280c088 Jiadong Zhu 2024-07-04 364 static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 178ad0e280c088 Jiadong Zhu 2024-07-04 365 uint32_t me_id, uint32_t pipe_id, 178ad0e280c088 Jiadong Zhu 2024-07-04 366 uint32_t queue_id, uint32_t vmid) 178ad0e280c088 Jiadong Zhu 2024-07-04 367 { 178ad0e280c088 Jiadong Zhu 2024-07-04 368 struct amdgpu_device *adev = mes->adev; 178ad0e280c088 Jiadong Zhu 2024-07-04 369 uint32_t value; 178ad0e280c088 Jiadong Zhu 2024-07-04 370 int i, r = 0; 178ad0e280c088 Jiadong Zhu 2024-07-04 371 178ad0e280c088 Jiadong Zhu 2024-07-04 372 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 178ad0e280c088 Jiadong Zhu 2024-07-04 373 178ad0e280c088 Jiadong Zhu 2024-07-04 374 if (queue_type == AMDGPU_RING_TYPE_GFX) { 178ad0e280c088 Jiadong Zhu 2024-07-04 375 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 178ad0e280c088 Jiadong Zhu 2024-07-04 376 me_id, pipe_id, queue_id, vmid); 178ad0e280c088 Jiadong Zhu 2024-07-04 377 178ad0e280c088 Jiadong Zhu 2024-07-04 378 mutex_lock(&adev->gfx.reset_sem_mutex); 178ad0e280c088 Jiadong Zhu 2024-07-04 379 gfx_v11_0_request_gfx_index_mutex(adev, true); 178ad0e280c088 Jiadong Zhu 2024-07-04 380 /* all se allow writes */ 178ad0e280c088 Jiadong Zhu 2024-07-04 381 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 178ad0e280c088 Jiadong Zhu 2024-07-04 382 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 178ad0e280c088 Jiadong Zhu 2024-07-04 383 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 178ad0e280c088 Jiadong Zhu 2024-07-04 384 if (pipe_id == 0) 178ad0e280c088 Jiadong Zhu 2024-07-04 385 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 178ad0e280c088 Jiadong Zhu 2024-07-04 386 else 178ad0e280c088 Jiadong Zhu 2024-07-04 387 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 178ad0e280c088 Jiadong Zhu 2024-07-04 388 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 178ad0e280c088 Jiadong Zhu 2024-07-04 389 gfx_v11_0_request_gfx_index_mutex(adev, false); 178ad0e280c088 Jiadong Zhu 2024-07-04 390 mutex_unlock(&adev->gfx.reset_sem_mutex); 178ad0e280c088 Jiadong Zhu 2024-07-04 391 178ad0e280c088 Jiadong Zhu 2024-07-04 392 mutex_lock(&adev->srbm_mutex); 178ad0e280c088 Jiadong Zhu 2024-07-04 393 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 178ad0e280c088 Jiadong Zhu 2024-07-04 394 /* wait till dequeue take effects */ 178ad0e280c088 Jiadong Zhu 2024-07-04 395 for (i = 0; i < adev->usec_timeout; i++) { 178ad0e280c088 Jiadong Zhu 2024-07-04 396 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 178ad0e280c088 Jiadong Zhu 2024-07-04 397 break; 178ad0e280c088 Jiadong Zhu 2024-07-04 398 udelay(1); 178ad0e280c088 Jiadong Zhu 2024-07-04 399 } 178ad0e280c088 Jiadong Zhu 2024-07-04 400 if (i >= adev->usec_timeout) { 178ad0e280c088 Jiadong Zhu 2024-07-04 401 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 178ad0e280c088 Jiadong Zhu 2024-07-04 402 r = -ETIMEDOUT; 178ad0e280c088 Jiadong Zhu 2024-07-04 403 } 178ad0e280c088 Jiadong Zhu 2024-07-04 404 178ad0e280c088 Jiadong Zhu 2024-07-04 405 soc21_grbm_select(adev, 0, 0, 0, 0); 178ad0e280c088 Jiadong Zhu 2024-07-04 406 mutex_unlock(&adev->srbm_mutex); 178ad0e280c088 Jiadong Zhu 2024-07-04 407 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 178ad0e280c088 Jiadong Zhu 2024-07-04 408 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 178ad0e280c088 Jiadong Zhu 2024-07-04 409 me_id, pipe_id, queue_id); 178ad0e280c088 Jiadong Zhu 2024-07-04 410 mutex_lock(&adev->srbm_mutex); 178ad0e280c088 Jiadong Zhu 2024-07-04 411 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 178ad0e280c088 Jiadong Zhu 2024-07-04 412 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 178ad0e280c088 Jiadong Zhu 2024-07-04 413 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 178ad0e280c088 Jiadong Zhu 2024-07-04 414 178ad0e280c088 Jiadong Zhu 2024-07-04 415 /* wait till dequeue take effects */ 178ad0e280c088 Jiadong Zhu 2024-07-04 @416 for (i = 0; i < adev->usec_timeout; i++) { 178ad0e280c088 Jiadong Zhu 2024-07-04 417 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 178ad0e280c088 Jiadong Zhu 2024-07-04 418 break; 178ad0e280c088 Jiadong Zhu 2024-07-04 419 udelay(1); 178ad0e280c088 Jiadong Zhu 2024-07-04 420 } 178ad0e280c088 Jiadong Zhu 2024-07-04 421 if (i >= adev->usec_timeout) { 178ad0e280c088 Jiadong Zhu 2024-07-04 422 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 178ad0e280c088 Jiadong Zhu 2024-07-04 423 r = -ETIMEDOUT; 178ad0e280c088 Jiadong Zhu 2024-07-04 424 } 178ad0e280c088 Jiadong Zhu 2024-07-04 425 soc21_grbm_select(adev, 0, 0, 0, 0); 178ad0e280c088 Jiadong Zhu 2024-07-04 426 mutex_unlock(&adev->srbm_mutex); 178ad0e280c088 Jiadong Zhu 2024-07-04 427 } 178ad0e280c088 Jiadong Zhu 2024-07-04 428 178ad0e280c088 Jiadong Zhu 2024-07-04 429 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 178ad0e280c088 Jiadong Zhu 2024-07-04 430 return r; 178ad0e280c088 Jiadong Zhu 2024-07-04 431 } 178ad0e280c088 Jiadong Zhu 2024-07-04 432 :::::: The code at line 416 was first introduced by commit :::::: 178ad0e280c088f5abfa61793cb992fa120d1830 drm/amdgpu/mes11: implement mmio queue reset for gfx11 :::::: TO: Jiadong Zhu <Jiadong.Zhu@xxxxxxx> :::::: CC: Alex Deucher <alexander.deucher@xxxxxxx> -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki
