Le 11/06/2024 à 18:10, Oscar Salvador a écrit : > [Vous ne recevez pas souvent de courriers de osalvador@xxxxxxx. D?couvrez pourquoi ceci est important ? https://aka.ms/LearnAboutSenderIdentification ] > > On Tue, Jun 11, 2024 at 11:20:01AM -0400, Peter Xu wrote: >> On Tue, Jun 11, 2024 at 05:08:45PM +0200, Oscar Salvador wrote: >>> The problem is that we do not have spare bits for 8xx to mark these ptes >>> as cont-ptes or mark them pte as 8MB, so I do not see a clear path on how >>> we could remove huge_ptep_get for 8xx. >> >> Right, I remember I thought about this too when I initially looked at one >> previous version of the series, I didn't come up yet with a good solution, >> but I guess we probably need to get rid of hugepd first anyway. We may >> somehow still need to identify this is a 8M large leaf, and I guess this is >> again the only special case where contpte can go over >1 pmds. > > Yes, we definitely need first to get rid of hugepd, which is a huge > step, and one step closer to our goal, but at some point we will have to > see what can we do about 8MB cont-ptes for 8xx and how to mark them, > so ptep_get can work the same way as e.g: arm64 > (ptep_get->contpte_ptep_get). > > @Christophe: Can you think of a way to flag those ptes? (e.g: a > combination of bits etc) We have space available in PMD if we need more flags, but in PTE I can't see anything possible without additional churn that would require additional instructions in TLB miss handlers, which is what I want to avoid most. Bits mapped to HW PTE: #define _PAGE_PRESENT 0x0001 /* V: Page is valid */ #define _PAGE_NO_CACHE 0x0002 /* CI: cache inhibit */ #define _PAGE_SH 0x0004 /* SH: No ASID (context) compare */ #define _PAGE_SPS 0x0008 /* SPS: Small Page Size (1 if 16k, 512k or 8M)*/ #define _PAGE_DIRTY 0x0100 /* C: page changed */ #define _PAGE_NA 0x0200 /* Supervisor NA, User no access */ #define _PAGE_RO 0x0600 /* Supervisor RO, User no access */ SW bits masked out in TLB miss handler: #define _PAGE_GUARDED 0x0010 /* Copied to L1 G entry in DTLB */ #define _PAGE_ACCESSED 0x0020 /* Copied to L1 APG 1 entry in I/DTLB */ #define _PAGE_EXEC 0x0040 /* Copied to PP (bit 21) in ITLB */ #define _PAGE_SPECIAL 0x0080 /* SW entry */ #define _PAGE_HUGE 0x0800 /* Copied to L1 PS bit 29 */ All bits are used. The only thing would could do but that would have a performance cost is to retrieve _PAGE_SH from the PMD and use that bit for something else. But I was maybe thinking another way. Lets take the exemple of pmd_write() helper: #define pmd_write(pmd) pte_write(pmd_pte(pmd)) At the time being we have static inline pte_t pmd_pte(pmd_t pmd) { return __pte(pmd_val(pmd)); } But what about something like static inline pte_t pmd_pte(pmd_t pmd) { return *(pte_t *)pmd_page_vaddr(pmd); } Would it do the trick ? Of course it would require to carefully make sure all accesses are done through pmd_pte(). Would that work ? Christophe
