+static int ras2_check_pcc_chan(struct ras2_context *ras2_ctx)
+{
+ struct acpi_ras2_shared_memory __iomem *generic_comm_base = ras2_ctx->pcc_comm_addr;
+ ktime_t next_deadline = ktime_add(ktime_get(), ras2_ctx->deadline);
+
+ while (!ktime_after(ktime_get(), next_deadline)) {
+ /*
+ * As per ACPI spec, the PCC space wil be initialized by
+ * platform and should have set the command completion bit when
+ * PCC can be used by OSPM
+ */
+ if (readw_relaxed(&generic_comm_base->status) & RAS2_PCC_CMD_COMPLETE)
+ return 0;
We should consider adding error checking here. In a modification of this
driver in our enabling efforts, we are checking bit 2 in the status register
for errors. For example, in our FW, we will set bit 2 if you try to
disable an
already disabled scrub.
+ /*
+ * Reducing the bus traffic in case this loop takes longer than
+ * a few retries.
+ */
+ udelay(10);
+ }
+
+ return -EIO;
+}
