Hi Samuel, On Wed, Mar 27, 2024 at 12:51 PM Samuel Holland <samuel.holland@xxxxxxxxxx> wrote: > > Implementations affected by SiFive errata CIP-1200 have a bug which > forces the kernel to always use the global variant of the sfence.vma > instruction. When affected by this errata, do not attempt to flush a > range of addresses; each iteration of the loop would actually flush the > whole TLB instead. Instead, minimize the overall number of sfence.vma > instructions. > > Signed-off-by: Samuel Holland <samuel.holland@xxxxxxxxxx> > --- > > Changes in v6: > - Clarify the commit message for patch 8 based on ML discussion > > Changes in v4: > - Only set tlb_flush_all_threshold when CONFIG_MMU=y. > > Changes in v3: > - New patch for v3 > > arch/riscv/errata/sifive/errata.c | 5 +++++ > arch/riscv/include/asm/tlbflush.h | 2 ++ > arch/riscv/mm/tlbflush.c | 2 +- > 3 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c > index 3d9a32d791f7..716cfedad3a2 100644 > --- a/arch/riscv/errata/sifive/errata.c > +++ b/arch/riscv/errata/sifive/errata.c > @@ -42,6 +42,11 @@ static bool errata_cip_1200_check_func(unsigned long arch_id, unsigned long imp > return false; > if ((impid & 0xffffff) > 0x200630 || impid == 0x1200626) > return false; > + > +#ifdef CONFIG_MMU > + tlb_flush_all_threshold = 0; > +#endif > + > return true; > } > > diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h > index 463b615d7728..8e329721375b 100644 > --- a/arch/riscv/include/asm/tlbflush.h > +++ b/arch/riscv/include/asm/tlbflush.h > @@ -66,6 +66,8 @@ void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, > unsigned long uaddr); > void arch_flush_tlb_batched_pending(struct mm_struct *mm); > void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch); > + > +extern unsigned long tlb_flush_all_threshold; > #else /* CONFIG_MMU */ > #define local_flush_tlb_all() do { } while (0) > #endif /* CONFIG_MMU */ > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c > index ad7bdcfcc219..18af7b5053af 100644 > --- a/arch/riscv/mm/tlbflush.c > +++ b/arch/riscv/mm/tlbflush.c > @@ -11,7 +11,7 @@ > * Flush entire TLB if number of entries to be flushed is greater > * than the threshold below. > */ > -static unsigned long tlb_flush_all_threshold __read_mostly = 64; > +unsigned long tlb_flush_all_threshold __read_mostly = 64; > > static void local_flush_tlb_range_threshold_asid(unsigned long start, > unsigned long size, > -- > 2.43.1 > Reviewed-by: Yunhui Cui <cuiyunhui@xxxxxxxxxxxxx> Thanks, Yunhui