tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master head: 084c8e315db34b59d38d06e684b1a0dd07d30287 commit: 50d05a09e8474fa4768ffd39cce6af7f73cf003b [1141/1756] pwm: stm32: Fix for settings using period > UINT32_MAX config: sh-allyesconfig (https://download.01.org/0day-ci/archive/20240327/202403270305.ydvX9xq1-lkp@xxxxxxxxx/config) compiler: sh4-linux-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240327/202403270305.ydvX9xq1-lkp@xxxxxxxxx/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@xxxxxxxxx> | Closes: https://lore.kernel.org/oe-kbuild-all/202403270305.ydvX9xq1-lkp@xxxxxxxxx/ All errors (new ones prefixed by >>): drivers/pwm/pwm-stm32.c: In function 'stm32_pwm_probe': >> drivers/pwm/pwm-stm32.c:662:15: error: implicit declaration of function 'devm_clk_rate_exclusive_get'; did you mean 'clk_rate_exclusive_get'? [-Werror=implicit-function-declaration] 662 | ret = devm_clk_rate_exclusive_get(dev, priv->clk); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ | clk_rate_exclusive_get cc1: some warnings being treated as errors vim +662 drivers/pwm/pwm-stm32.c 627 628 static int stm32_pwm_probe(struct platform_device *pdev) 629 { 630 struct device *dev = &pdev->dev; 631 struct device_node *np = dev->of_node; 632 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); 633 struct pwm_chip *chip; 634 struct stm32_pwm *priv; 635 unsigned int npwm, num_enabled; 636 unsigned int i; 637 int ret; 638 639 npwm = stm32_pwm_detect_channels(ddata->regmap, &num_enabled); 640 641 chip = devm_pwmchip_alloc(dev, npwm, sizeof(*priv)); 642 if (IS_ERR(chip)) 643 return PTR_ERR(chip); 644 priv = to_stm32_pwm_dev(chip); 645 646 mutex_init(&priv->lock); 647 priv->regmap = ddata->regmap; 648 priv->clk = ddata->clk; 649 priv->max_arr = ddata->max_arr; 650 651 if (!priv->regmap || !priv->clk) 652 return dev_err_probe(dev, -EINVAL, "Failed to get %s\n", 653 priv->regmap ? "clk" : "regmap"); 654 655 ret = stm32_pwm_probe_breakinputs(priv, np); 656 if (ret) 657 return dev_err_probe(dev, ret, 658 "Failed to configure breakinputs\n"); 659 660 stm32_pwm_detect_complementary(priv); 661 > 662 ret = devm_clk_rate_exclusive_get(dev, priv->clk); 663 if (ret) 664 return dev_err_probe(dev, ret, "Failed to lock clock\n"); 665 666 /* 667 * With the clk running with not more than 1 GHz the calculations in 668 * .apply() won't overflow. 669 */ 670 if (clk_get_rate(priv->clk) > 1000000000) 671 return dev_err_probe(dev, -EINVAL, "Failed to lock clock\n"); 672 673 chip->ops = &stm32pwm_ops; 674 675 /* Initialize clock refcount to number of enabled PWM channels. */ 676 for (i = 0; i < num_enabled; i++) 677 clk_enable(priv->clk); 678 679 ret = devm_pwmchip_add(dev, chip); 680 if (ret < 0) 681 return dev_err_probe(dev, ret, 682 "Failed to register pwmchip\n"); 683 684 platform_set_drvdata(pdev, chip); 685 686 return 0; 687 } 688 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki
