On Thu, Feb 29, 2024 at 03:21:41PM -0800, Samuel Holland wrote: > Samuel Holland (13): > riscv: Flush the instruction cache during SMP bringup > riscv: Factor out page table TLB synchronization From here onwards, fails on 32-bit, bunch of implicit-function-declaration stuff. > riscv: Use IPIs for remote cache/TLB flushes by default > riscv: mm: Broadcast kernel TLB flushes only when needed > riscv: Only send remote fences when some other CPU is online > riscv: mm: Combine the SMP and UP TLB flush code > riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma > riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 > riscv: mm: Introduce cntx2asid/cntx2version helper macros > riscv: mm: Use a fixed layout for the MM context ID > riscv: mm: Make asid_bits a local variable > riscv: mm: Preserve global TLB entries when switching contexts > riscv: mm: Always use an ASID to flush mm contexts
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