On Tue, Jan 2, 2024 at 11:01 PM Samuel Holland
<samuel.holland@xxxxxxxxxx> wrote:
>
> If the CPU does not support multiple ASIDs, all MM contexts use ASID 0.
> In this case, it is still beneficial to flush the TLB by ASID, as the
> single-ASID variant of the sfence.vma instruction preserves TLB entries
> for global (kernel) pages.
>
> This optimization is recommended by the RISC-V privileged specification:
>
> If the implementation does not provide ASIDs, or software chooses
> to always use ASID 0, then after every satp write, software should
> execute SFENCE.VMA with rs1=x0. In the common case that no global
> translations have been modified, rs2 should be set to a register
> other than x0 but which contains the value zero, so that global
> translations are not flushed.
>
> It is not possible to apply this optimization when using the ASID
> allocator, because that code must flush the TLB for all ASIDs at once
> when incrementing the version number.
>
> Signed-off-by: Samuel Holland <samuel.holland@xxxxxxxxxx>
> ---
>
> (no changes since v1)
>
> arch/riscv/mm/context.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c
> index 43a8bc2d5af4..3ca9b653df7d 100644
> --- a/arch/riscv/mm/context.c
> +++ b/arch/riscv/mm/context.c
> @@ -200,7 +200,7 @@ static void set_mm_noasid(struct mm_struct *mm)
> {
> /* Switch the page table and blindly nuke entire local TLB */
> csr_write(CSR_SATP, virt_to_pfn(mm->pgd) | satp_mode);
> - local_flush_tlb_all();
> + local_flush_tlb_all_asid(0);
> }
>
> static inline void set_mm(struct mm_struct *prev,
> --
> 2.42.0
>
You can add:
Reviewed-by: Alexandre Ghiti <alexghiti@xxxxxxxxxxxx>
Thanks,
Alex
