On 04/12/2023 11:57, Christophe Leroy wrote: > > > Le 04/12/2023 à 12:46, Ryan Roberts a écrit : >> On 04/12/2023 11:25, Christophe Leroy wrote: >>> >>> >>> Le 04/12/2023 à 12:11, Ryan Roberts a écrit : >>>> On 03/12/2023 13:33, Christophe Leroy wrote: >>>>> >>>>> >>>>> Le 30/11/2023 à 22:30, Peter Xu a écrit : >>>>>> On Fri, Nov 24, 2023 at 11:07:51AM -0500, Peter Xu wrote: >>>>>>> On Fri, Nov 24, 2023 at 09:06:01AM +0000, Ryan Roberts wrote: >>>>>>>> I don't have any micro-benchmarks for GUP though, if that's your question. Is >>>>>>>> there an easy-to-use test I can run to get some numbers? I'd be happy to try it out. >>>>>>> >>>>>>> Thanks Ryan. Then nothing is needed to be tested if gup is not yet touched >>>>>>> from your side, afaict. I'll see whether I can provide some rough numbers >>>>>>> instead in the next post (I'll probably only be able to test it in a VM, >>>>>>> though, but hopefully that should still reflect mostly the truth). >>>>>> >>>>>> An update: I finished a round of 64K cont_pte test, in the slow gup micro >>>>>> benchmark I see ~15% perf degrade with this patchset applied on a VM on top >>>>>> of Apple M1. >>>>>> >>>>>> Frankly that's even less than I expected, considering not only how slow gup >>>>>> THP used to be, but also on the fact that that's a tight loop over slow >>>>>> gup, which in normal cases shouldn't happen: "present" ptes normally goes >>>>>> to fast-gup, while !present goes into a fault following it. I assume >>>>>> that's why nobody cared slow gup for THP before. I think adding cont_pte >>>>>> support shouldn't be very hard, but that will include making cont_pte idea >>>>>> global just for arm64 and riscv Svnapot. >>>>> >>>>> Is there any documentation on what cont_pte is ? I have always wondered >>>>> if it could also fit powerpc 8xx need ? >>>> >>>> pte_cont() (and pte_mkcont() and pte_mknoncont()) test and manipulte the >>>> "contiguous bit" in the arm64 PTE entries. Those helpers are arm64-specific >>>> (AFAIK). The contiguous bit is a hint to the HW to tell it that a block of PTEs >>>> are mapping a physically contiguous and naturally aligned piece of memory. The >>>> HW can use this to coalesce entries in the TLB. When using 4K base pages, the >>>> contpte size is 64K (16 PTEs). For 16K base pages, its 2M (128 PTEs) and for 64K >>>> base pages, its 2M (32 PTEs). >>>> >>>>> >>>>> On powerpc, for 16k pages, we have to define 4 consecutive PTEs. All 4 >>>>> PTE are flagged with the SPS bit telling it's a 16k pages, but for TLB >>>>> misses the HW needs one entrie for each 4k fragment. >>>> >>>> From that description, it sounds like the SPS bit might be similar to arm64 >>>> contiguous bit? Although sounds like you are currently using it in a slightly >>>> different way - telling kernel that the base page is 16K but mapping each 16K >>>> page with 4x 4K entries (plus the SPS bit set)? >>> >>> Yes it's both. >>> >>> When the base page is 16k, there are 4x 4k entries (with SPS bit set) in >>> the page table, and pte_t is a table of 4 'unsigned long' >>> >>> When the base page is 4k, there is a 16k hugepage size, which is the >>> same 4x 4k entries with SPS bit set. >>> >>> So it looks similar to the contiguous bit. >>> >>> >>> And by extension, the same principle is used for 512k hugepages, the bit >>> _PAGE_HUGE is copied by the TLB miss handler into the lower bit of PS, >>> PS being as follows: >>> - 00 Small (4 Kbyte or 16 Kbyte) >>> - 01 512 Kbyte >>> - 10 Reserved >>> - 11 8 Mbyte >>> >>> So as PMD size is 4M, 512k pages are 128 identical consecutive entries >>> in the page table. >>> >>> I which I could have THP with 16k or 512k pages. >> >> Then you have come to the right place! :) >> >> https://lore.kernel.org/linux-mm/20231204102027.57185-1-ryan.roberts@xxxxxxx/ >> > > That looks great. That series only modifies core mm/ . > No changes needed in arch ? Will it work on powerpc without any > change/additions to arch code ? Yes there are also changes needed in arch; I have a separate series for arm64, which transparently manages the contiguous bit when it sees appropriate PTEs: https://lore.kernel.org/linux-arm-kernel/20231204105440.61448-1-ryan.roberts@xxxxxxx/ > > Well, I'll try it soon. > > Christophe
