While reviewing Alexandre Ghiti's "riscv: tlb flush improvements" series[1], I noticed that most TLB flush functions end up as a call to local_flush_tlb_all() when SMP is disabled. This series resolves that. Along the way, I realized that we should be using single-ASID flushes wherever possible, so I implemented that as well. [1]: https://lore.kernel.org/linux-riscv/20231030133027.19542-1-alexghiti@xxxxxxxxxxxx/ Changes in v3: - Fixed a performance regression caused by executing sfence.vma in a loop on implementations affected by SiFive CIP-1200 - Rebased on v6.7-rc1 Changes in v2: - Move the SMP/UP merge earlier in the series to avoid build issues - Make a copy of __flush_tlb_range() instead of adding ifdefs inside - local_flush_tlb_all() is the only function used on !MMU (smpboot.c) Samuel Holland (8): riscv: mm: Combine the SMP and UP TLB flush code riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: mm: Use a fixed layout for the MM context ID riscv: mm: Make asid_bits a local variable riscv: mm: Preserve global TLB entries when switching contexts riscv: mm: Always use ASID to flush MM contexts arch/riscv/errata/sifive/errata.c | 3 ++ arch/riscv/include/asm/errata_list.h | 12 ++++++- arch/riscv/include/asm/mmu.h | 3 ++ arch/riscv/include/asm/mmu_context.h | 2 -- arch/riscv/include/asm/tlbflush.h | 54 ++++++++++++++-------------- arch/riscv/mm/Makefile | 5 +-- arch/riscv/mm/context.c | 26 ++++++-------- arch/riscv/mm/tlbflush.c | 41 ++++++++------------- 8 files changed, 70 insertions(+), 76 deletions(-) -- 2.42.0
