On 2023-10-26 17:35, Steven Rostedt wrote:
On Thu, 26 Oct 2023 15:20:22 -0400 Steven Rostedt <rostedt@xxxxxxxxxxx> wrote:Anyway, I changed the code to use: static inline unsigned clrbit(volatile unsigned *ptr) { unsigned ret; asm volatile("andb %b1,%0" : "+m" (*(volatile char *)ptr) : "iq" (0x2) : "memory"); ret = *ptr; *ptr = 0; return ret; }Mathieu also told me that glibc's rseq has some extra padding at the end, that happens to be big enough to hold this feature. That means you can run the code without adding: GLIBC_TUNABLES=glibc.pthread.rseq=0 Attached is the updated test program.
I think you'll want to modify the semantic of your "cr_flags" field so it supports nested locks as well. You can change this cr_flags for a nesting counter. The "yield" bit could be one of the bits of that counter (e.g. lowest bit). Therefore extend() become add 0x2, and unextend() become a sub 0x2, and you can check the lowest bit for yield hint. Thanks, Mathieu -- Mathieu Desnoyers EfficiOS Inc. https://www.efficios.com
