On Fri, Sep 29, 2023 at 03:52:22PM -0700, Sami Tolvanen wrote: > On Fri, Sep 29, 2023 at 2:54 PM Kees Cook <keescook@xxxxxxxxxxxx> wrote: > > > > On Fri, Sep 29, 2023 at 09:11:58PM +0000, Sami Tolvanen wrote: > > > ARCH_MMAP_RND_BITS_MAX is based on Sv39, which leaves a few > > > potential bits of mmap randomness on the table if we end up enabling > > > 4/5-level paging. Update mmap_rnd_bits_max to take the final address > > > space size into account. This increases mmap_rnd_bits_max from 24 to > > > 33 with Sv48/57. > > > > > > Signed-off-by: Sami Tolvanen <samitolvanen@xxxxxxxxxx> > > > > I like this. Is RISCV the only arch where the paging level can be chosen > > at boot time? > > I haven't seen this elsewhere, but I also haven't looked at all the > other architectures that closely. arm64 does something interesting > with ARM64_VA_BITS_52, but I think we can still handle that in > Kconfig. AFAIU, x86-64 can do this also: no4lvl [RISCV] Disable 4-level and 5-level paging modes. Forces kernel to use 3-level paging instead. no5lvl [X86-64,RISCV] Disable 5-level paging mode. Forces kernel to use 4-level paging instead.
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