Hi Conor, On Thu, Aug 31, 2023 at 12:34 PM Conor Dooley <conor.dooley@xxxxxxxxxxxxx> wrote: > > On Thu, Aug 31, 2023 at 12:22:50PM +0100, Lad, Prabhakar wrote: > > Hi Conor, > > > > On Thu, Aug 31, 2023 at 10:44 AM Conor Dooley > > <conor.dooley@xxxxxxxxxxxxx> wrote: > > > > > > On Thu, Aug 31, 2023 at 04:52:00PM +0800, kernel test robot wrote: > > > > tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master > > > > head: a47fc304d2b678db1a5d760a7d644dac9b067752 > > > > commit: f2863f30d1b05e5ecf61c063609cb974954d47f8 [13230/13643] riscv: errata: Add Andes alternative ports > > > > config: riscv-randconfig-001-20230831 (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@xxxxxxxxx/config) > > > > compiler: riscv64-linux-gcc (GCC) 13.2.0 > > > > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230831/202308311610.ec6bm2G8-lkp@xxxxxxxxx/reproduce) > > > > > > > > If you fix the issue in a separate patch/commit (i.e. not just a new version of > > > > the same patch/commit), kindly add following tags > > > > | Reported-by: kernel test robot <lkp@xxxxxxxxx> > > > > | Closes: https://lore.kernel.org/oe-kbuild-all/202308311610.ec6bm2G8-lkp@xxxxxxxxx/ > > > > > > > > All error/warnings (new ones prefixed by >>): > > > > > > > > arch/riscv/errata/andes/errata.c: In function 'ax45mp_iocp_sw_workaround': > > > > >> arch/riscv/errata/andes/errata.c:29:23: error: storage size of 'ret' isn't known > > > > 29 | struct sbiret ret; > > > > | ^~~ > > > > >> arch/riscv/errata/andes/errata.c:35:15: error: implicit declaration of function 'sbi_ecall' [-Werror=implicit-function-declaration] > > > > 35 | ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND, > > > > | ^~~~~~~~~ > > > > >> arch/riscv/errata/andes/errata.c:29:23: warning: unused variable 'ret' [-Wunused-variable] > > > > 29 | struct sbiret ret; > > > > | ^~~ > > > > cc1: some warnings being treated as errors > > > > > > > > > > > > vim +29 arch/riscv/errata/andes/errata.c > > > > > > > > 26 > > > > 27 static long ax45mp_iocp_sw_workaround(void) > > > > 28 { > > > > > 29 struct sbiret ret; > > > > 30 > > > > 31 /* > > > > 32 * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and > > > > 33 * cache is controllable only then CMO will be applied to the platform. > > > > 34 */ > > > > > 35 ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND, > > > > 36 0, 0, 0, 0, 0, 0); > > > > 37 > > > > 38 return ret.error ? 0 : ret.value; > > > > 39 } > > > > 40 > > > > > > Looks like the config doesn't enable SBI, so ERRATA_ANDES_CMO will need > > > to grow a dependency on RISCV_SBI. > > I think adding dependency for RISCV_SBI on ERRATA_ANDES would be a good idea. > > > > While at it I am seeing below warnings with this randconfig: > > WARNING: unmet direct dependencies detected for ERRATA_ANDES_CMO > > Depends on [n]: ERRATA_ANDES [=y] && MMU [=n] && ARCH_R9A07G043 [=y] > > Selected by [y]: > > - ARCH_R9A07G043 [=y] && SOC_RENESAS [=y] && RISCV [=y] > > > > WARNING: unmet direct dependencies detected for AX45MP_L2_CACHE > > Depends on [n]: RISCV_DMA_NONCOHERENT [=n] > > Selected by [y]: > > - ARCH_R9A07G043 [=y] && SOC_RENESAS [=y] && RISCV [=y] > > configuration written to .config > > > > *** End of the configuration. > > *** Execute 'make' to start the build or try 'make help'. > > > > For which I will send the below fix: > > --- a/drivers/soc/renesas/Kconfig > > +++ b/drivers/soc/renesas/Kconfig > > @@ -334,10 +334,10 @@ if RISCV > > config ARCH_R9A07G043 > > bool "RISC-V Platform support for RZ/Five" > > select ARCH_RZG2L > > - select AX45MP_L2_CACHE > > + imply AX45MP_L2_CACHE > > select DMA_GLOBAL_POOL > > - select ERRATA_ANDES > > - select ERRATA_ANDES_CMO > > + imply ERRATA_ANDES > > + imply ERRATA_ANDES_CMO > > help > > This enables support for the Renesas RZ/Five SoC. > > I've only ever heard bad things from Arnd about using imply. > > Why don't you just make the erratum config option select > RISCV_DMA_NONCOHERENT, just like the THEAD_CMO erratum does? > The cache driver should probably then depend on the erratum Kconfig > option, since there's no point in having it otherwise? > Agreed. I have the below proposal: --------------------------------------- diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 92c779764b27..672480f4f983 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -3,6 +3,7 @@ menu "CPU errata selection" config ERRATA_ANDES bool "Andes AX45MP errata" depends on RISCV_ALTERNATIVE + depends on RISCV_SBI help All Andes errata Kconfig depend on this Kconfig. Disabling this Kconfig will disable all Andes errata. Please say "Y" @@ -12,7 +13,7 @@ config ERRATA_ANDES config ERRATA_ANDES_CMO bool "Apply Andes cache management errata" - depends on ERRATA_ANDES && MMU && ARCH_R9A07G043 + depends on ERRATA_ANDES && MMU select RISCV_DMA_NONCOHERENT default y help diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index a57677f908f3..14d0ff5ec71b 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -3,7 +3,7 @@ menu "Cache Drivers" config AX45MP_L2_CACHE bool "Andes Technology AX45MP L2 Cache controller" - depends on RISCV_DMA_NONCOHERENT + depends on ERRATA_ANDES_CMO select RISCV_NONSTANDARD_CACHE_OPS help Support for the L2 cache controller on Andes Technology AX45MP platforms. diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 67604f24973e..4f14fa149985 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -333,11 +333,9 @@ if RISCV config ARCH_R9A07G043 bool "RISC-V Platform support for RZ/Five" + depends on AX45MP_L2_CACHE select ARCH_RZG2L - select AX45MP_L2_CACHE select DMA_GLOBAL_POOL - select ERRATA_ANDES - select ERRATA_ANDES_CMO help This enables support for the Renesas RZ/Five SoC. Cheers, Prabhakar
