On Tue, Jul 25 2023 at 10:06:01 AM +0800, Huacai Chen wrote: > On Sun, Jul 23, 2023 at 3:17 PM Enze Li <lienze@xxxxxxxxxx> wrote: >> >> On Fri, Jul 21 2023 at 10:21:38 AM +0800, Huacai Chen wrote: >> >> > On Fri, Jul 21, 2023 at 10:12 AM Enze Li <lienze@xxxxxxxxxx> wrote: >> >> >> >> On Wed, Jul 19 2023 at 11:29:37 PM +0800, Huacai Chen wrote: >> >> >> >> > Hi, Enze, >> >> > >> >> > On Wed, Jul 19, 2023 at 4:34 PM Enze Li <lienze@xxxxxxxxxx> wrote: <snip> >> I've also tried to include mm_types.h in advance, but in this case that >> doesn't work because the _LINUX_MM_TYPES_H macro already exists. >> The "forward declaration" was also taken into account, in the end it was >> found to be unavailable as well. >> >> In summary, I'm afraid that rewriting tlb_virt_to_page in asm/page.h as >> a macro or inline function is not possible. The root case of this is >> that both 'struct mm_struct' and 'virt_to_kpte' belong to high-level >> data structures, and if they are referenced in asm/page.h at the >> low-level, dependency problems arise. >> >> Anyway, we can at least define it as a normal function in asm/pgtable.h, >> is that Okay with you? >> >> It may be a bit wordy, so please bear with me. In addition, all of the >> above is my understanding, am I missing something? > Well, you can define the helpers in .c files at present, but I have > another question. > > Though other archs (e.g., RISC-V) have no DMW addresses, they still > have linear area. In other words, both LoongArch and RISC-V have > linear area and vmalloc-like areas. The only difference is LoongArch's > linear area is DMW-mapped but RISC-V's linear area is TLB-mapped. > > For linear area, the translation is pfn_to_page(virt_to_pfn(kaddr)), > no matter LoongArch or RISC-V; > For vmalloc-like areas, the translation is > pte_page(*virt_to_kpte(kaddr)), no matter LoongArch or RISC-V. > Hi Huacai, Thanks for your reply. > My question is: why RISC-V only care about the linear area for > virt_to_page(), but you are caring about the vmalloc-like areas? This patch is a preparation to make LoongArch support KFENCE. One of the core principles of KFENCE is that pages are tagged in the PTE and then synchronized to the TLB. When the MMU detects an improper access, it can generate an interrupt signal, which is subsequently handled by a handler function (kfence_handle_page_fault) provided by KFENCE. In short, KFENCE requires the support of the TLB. There's no need to take this into account on RISC-V because TLB mapping is already supported in linear area. Best Regards, Enze > > Huacai <snip>
