On Tue, Jul 18, 2023 at 11:17:59AM -0700, Andrew Morton wrote: > On Tue, 18 Jul 2023 17:56:17 +1000 Alistair Popple <apopple@xxxxxxxxxx> wrote: > > > The arch_invalidate_secondary_tlbs() is an architecture specific mmu > > notifier used to keep the TLB of secondary MMUs such as an IOMMU in > > sync with the CPU page tables. Currently it is called from separate > > code paths to the main CPU TLB invalidations. This can lead to a > > secondary TLB not getting invalidated when required and makes it hard > > to reason about when exactly the secondary TLB is invalidated. > > > > To fix this move the notifier call to the architecture specific TLB > > maintenance functions for architectures that have secondary MMUs > > requiring explicit software invalidations. > > > > This fixes a SMMU bug on ARM64. On ARM64 PTE permission upgrades > > require a TLB invalidation. This invalidation is done by the > > architecutre specific ptep_set_access_flags() which calls > > flush_tlb_page() if required. However this doesn't call the notifier > > resulting in infinite faults being generated by devices using the SMMU > > if it has previously cached a read-only PTE in it's TLB. > > This sounds like a pretty serious bug. Can it happen in current > released kernels? If so, is a -stable backport needed? There are currently no in-kernel drivers using the IOMMU SVA API, so the impact for -stable is sort of muted. But it is serious if you are unlucky to hit it. Jason
