On Tue, May 30, 2023 at 06:05:41PM +1000, Alistair Popple wrote: > > >> As no notification is sent and the SMMU does not snoop TLB invalidates > >> it will continue to return read-only entries to a device even though > >> the CPU page table contains a writable entry. This leads to a > >> continually faulting device and no way of handling the fault. > > > > Doesn't the fault generate a PRI/etc? If we get a PRI maybe we should > > just have the iommu driver push an iotlb invalidation command before > > it acks it? PRI is already really slow so I'm not sure a pipelined > > invalidation is going to be a problem? Does the SMMU architecture > > permit negative caching which would suggest we need it anyhow? > > Yes, SMMU architecture (which matches the ARM architecture in regards to > TLB maintenance requirements) permits negative caching of some mapping > attributes including the read-only attribute. Hence without the flushing > we fault continuously. Sounds like a straight up SMMU bug, invalidate the cache after resolving the PRI event. Jason
