On 2023-05-24 22:33:36, Peter Zijlstra wrote:
> On Wed, May 24, 2023 at 01:16:03PM -0700, Sean Christopherson wrote:
>
> > Atomics aren't memory barriers on all architectures, e.g. see the various
> > definitions of smp_mb__after_atomic().
> >
> > Even if atomic operations did provide barriers, using an atomic would be overkill
> > and a net negative. On strongly ordered architectures like x86, memory barriers are
> > just compiler barriers, whereas atomics may be more expensive.
>
> Not quite, smp_{r,w}mb() and smp_mb__{before,after}_atomic() are
> compiler barriers on the TSO archs, but smp_mb() very much isn't. TSO
> still allows stores to be delayed vs later loads (iow it doesn't pretend
> to hide the store buffer).
>
> > Of course, the only
> > accesses outside of mmu_lock are reads, so on x86 that "atomic" access is just a
> > READ_ONCE() load, but that's not the case for all architectures.
>
> This is true on *all* archs. atomic_set() and atomic_read() are no more
> and no less than WRITE_ONCE() / READ_ONCE().
>
> > Anyways, the point is that atomics and memory barriers are different things that
> > serve different purposes.
>
> This is true; esp. on the weakly ordered architectures where atomics do
> not naturally imply any ordering.
Thanks for the information, everyone.
