> On Apr 1, 2023, at 3:51 AM, Gregory Price <gregory.price@xxxxxxxxxxxx> wrote: > > On Tue, Apr 04, 2023 at 05:58:05PM +0000, Adam Manzanares wrote: >> On Tue, Apr 04, 2023 at 11:31:08AM +0300, Mike Rapoport wrote: >>> >>> The point of zswap IIUC is to have small and fast swap device and >>> compression is required to better utilize DRAM capacity at expense of CPU >>> time. >>> >>> Presuming CXL memory will have larger capacity than DRAM, why not skip the >>> compression and use CXL as a swap device directly? >> >> I like to shy away from saying CXL memory should be used for swap. I see a >> swap device as storing pages in a manner that is no longer directly addressable >> by the cpu. >> >> Migrating pages to a CXL device is a reasonable approach and I believe we >> have the ability to do this in the page reclaim code. >> > > The argument is "why do you need swap if memory itself is elastic", and > I think there are open questions about how performant using large > amounts of high-latency memory is. > > Think 1us-1.5us+ cross-rack attached memory. > > Does it make sense to use that as CPU-addressible and migrate it on > first use? Isn't that just swap with more steps? What happens if we > just use it as swap, is the performance all that different? > > I think there's a reasonable argument for exploring the idea at the > higher ends of the latency spectrum. And the simplicity of using an > existing system (swap) to implement a form of proto-tiering is rather > attractive in my opinion. > I think the problem with swap that we need to take into account the additional latency of swap-in/swap-out logic. I assume that this logic is expensive enough. And if we considering the huge graph, for example, I am afraid the swap-in/swap-out logic could be expensive. So, the question here is about use-case. Which use-case could have benefits to employ the swap as a big space of high-latency memory? I see your point that such swap could be faster than persistent storage. But which use-case can be happy user of this space of high-latency memory? Thanks, Slava.
