On Mon, Feb 20, 2023 at 11:38 PM Zhu Yanjun <zyjzyj2000@xxxxxxxxx> wrote: > > On Tue, Feb 21, 2023 at 12:32 AM Pasha Tatashin > <pasha.tatashin@xxxxxxxxxx> wrote: > > > > Hello, > > > > As a part of an ongoing work of replacing some containerized work load > > with virtual machines within Google, I have worked on making the > > memory translations faster. > > > > I would like to propose the following topic for this year's LSF/MM/BPF: > > > > Discuss a set of techniques that can improve the guest performance, > > memory footprint overhead, observability, and manageability of virtual > > machines by hypervirtualizing the guest memory to the extreme. The end > > goal is to allow very lightweight virtual machines to be closer in > > performance to the containers. > > > > The following items are going to be discussed in this topic: > > - Reducing the cost of SLAT page table translations. > > Intel's implementation of SLAT, known as Extended Page Table (EPT), > was introduced in the Nehalem microarchitecture found in certain Core > i7, Core i5, and Core i3 processors. > ARM's virtualization extensions support SLAT, known as Stage-2 > page-tables provided by a Stage-2 MMU. The guest uses the Stage-1 MMU. > Support was added as optional in the ARMv7ve architecture and is also > supported in the ARMv8 (32-bit and 64-bit) architectures. > I am interested in this. Hope we have a better solution to reduce the > cost of SLAT. Hi Zhu, Please take a look at my previous reply to Gavin Shan where I clarify the SLAT performance improvements. Thanks, Pasha > > > - Reducing the memory footprint overhead. > > - Reducing the memory management overhead. > > - Increasing the observability of guest memory. > >
