On Thu, Jan 19, 2023 at 11:42:26AM -0800, James Houghton wrote: > - We avoid problems related to compound PTEs (the problem being: two > threads racing to populate a contiguous and non-contiguous PTE that > take up the same space could lead to user-detectable incorrect > behavior. This isn't hard to fix; it will be when I send the arm64 > patches up.) Could you elaborate this one a bit more? > This might seem kind of contrived, but let's say you have a VM with 1T > of memory, and you find 100 memory errors all in different 1G pages > over the life of this VM (years, potentially). Having 10% of your > memory be 4K-mapped is definitely worse than having 10% be 2M-mapped > (lost performance and increased memory overhead). There might be other > cases in the future where being able to have intermediate mapping > sizes could be helpful. This is not the norm, or is it? How the possibility of bad pages can distribute over hosts over years? This can definitely affect how we should target the intermediate level mappings. Thanks, -- Peter Xu
