On 11/7/22 09:14, Kirill A. Shutemov wrote:
> --- a/arch/x86/mm/tlb.c
> +++ b/arch/x86/mm/tlb.c
> @@ -561,7 +561,15 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
> if (real_prev == next) {
> VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) !=
> next->context.ctx_id);
> - VM_WARN_ON(prev_lam != new_lam);
> +
> + /*
> + * 'prev_lam' does not necessary match 'new_lam' here. In case
> + * of race with LAM enabling, the updated 'lam_cr3_mask' can be
> + * been before LAM-enabling IPI kicks in.
> + *
> + * The race is harmless: it is okay to update CR3 with new LAM
> + * mode. The IPI will rewrite CR3 shortly.
> + */
So, let's do something like this in switch_mm_irqs_off():
/* Not actually switching mm's */
VM_WARN_ON(this_cpu_read(cpu_tlbstate....
/*
* If this races with another thread that enables
* lam, 'new_lam' might not match 'prev_lam'.
*/
Then, in enable_lam_func(), something like this:
/*
* Update CR3 to get LAM active on the CPU
*
* This might not actually need to update CR3 if a context
* switch happened between updating 'lam_cr3_mask' and
* running this IPI handler. Update it unconditionally for
* simplicity.
*/
cr3 = __read_cr3();
cr3 &= ~(X86_CR3_LAM_U48 | X86_CR3_LAM_U57);
cr3 |= lam_mask;
write_cr3(cr3);
set_tlbstate_cr3_lam_mask(lam_mask);
I'd much rather get folks thinking about IPI races in the IPI handler
rather than thinking about the IPI handler in the context switch path.
It's kinda silly to be describing the occasional superfluous
enable_lam_func() activity from switch_mm_irqs_off().
