From: Guo Ren <guoren@xxxxxxxxxxxxxxxxx>
RISC-V follows the arm64 flush_icache_pte mechanism and also includes
its bug. The patch ensures that instructions are observable in a new
mapping. For more details, see 588a513d3425 ("arm64: Fix race condition
on PG_dcache_clean in __sync_icache_dcache()").
Signed-off-by: Guo Ren <guoren@xxxxxxxxxxxxxxxxx>
Signed-off-by: Guo Ren <guoren@xxxxxxxxxx>
Cc: Catalin Marinas <catalin.marinas@xxxxxxx>
Cc: Will Deacon <will@xxxxxxxxxx>
Cc: Steven Price <steven.price@xxxxxxx>
---
arch/riscv/mm/cacheflush.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index 6cb7d96ad9c7..7c9f97fa3938 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -82,7 +82,9 @@ void flush_icache_pte(pte_t pte)
{
struct page *page = pte_page(pte);
- if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+ if (!test_bit(PG_dcache_clean, &page->flags)) {
flush_icache_all();
+ set_bit(PG_dcache_clean, &page->flags);
+ }
}
#endif /* CONFIG_MMU */
--
2.36.1
