On Tue, Jun 28, 2022, at 5:53 PM, Kirill A. Shutemov wrote: > On Tue, Jun 28, 2022 at 04:42:40PM -0700, Andy Lutomirski wrote: >> On 6/10/22 07:35, Kirill A. Shutemov wrote: >> >> > + /* Update CR3 to get LAM active */ >> > + switch_mm(current->mm, current->mm, current); >> >> Can you at least justify this oddity? When changing an LDT, we use a >> dedicated mechanism. Is there a significant benefit to abusing switch_mm >> for this? > > I'm not sure I follow. LAM mode is set in CR3. switch_mm() has to handle > it anyway to context switch. Why do you consider it abuse? > >> >> Also, why can't we enable LAM on a multithreaded process? We can change an >> LDT, and the code isn't even particularly complicated. > > I reworked this in v4[1] and it allows multithreaded processes. Have you > got that version? > > Intel had issue with mail server, but I assumed it didn't affect my > patchset since I see it in the archive. > I didn’t notice it. Not quite sure what the issue was. Could just be incompetence on my part. I think that’s the right idea, except that I think you shouldn’t use switch_mm for this. Just update the LAM bits directly. Once you read mm_cpumask, you should be guaranteed (see next paragraph) that, for each CPU that isn’t in the set, if it switches to the new mm, it will notice the new LAM. I say “should be” because I think smp_wmb() is insufficient. You’re ordering a write with a subsequent read, which needs smp_mb(). > [1] > https://lore.kernel.org/all/20220622162230.83474-1-kirill.shutemov@xxxxxxxxxxxxxxx/ > > -- > Kirill A. Shutemov
