From: Christophe Leroy > Sent: 17 June 2022 12:06 > > Le 17/06/2022 à 09:58, Geert Uytterhoeven a écrit : > >> But it then causes pointless problems when people can't really rely on > >> more than 32 bits for atomic bit operations, and on 64-bit > >> architectures we unnecessarily use "long" and waste the upper bits. > > > > Well, atomic works up to native word size, i.e. long. > > > > powerpc64 has a pair of instructions to perform 128bits atomic > operations : lqarx / stqcx. As does x86-64 (and 32bit has a 64bit atomic compare+exchange). Annoyingly the x86-64 doesn't have 128bit read/write register pair instructions that would generate a 128bit PCIe TLP. You can use AVX instructions to generate large TLP - but not in the linux kernel - you want 1 big register. Even the humble 68020 has a cas2 instruction that will do a 64bit atomic operation. I did manage to use it once, but it is easier to disable interrupts. I'm not sure how many SMP 68020 systems were ever built. You'd need a matched pair of cpu (or extreme care) since it tends to stack microcode data on mid-instruction faults. David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)
