On Sun, May 1, 2022 at 11:35 AM Dan Williams <dan.j.williams@xxxxxxxxx> wrote: > > On Fri, Apr 29, 2022 at 8:59 PM Yang Shi <shy828301@xxxxxxxxx> wrote: > > > > Hi Wei, > > > > Thanks for the nice writing. Please see the below inline comments. > > > > On Fri, Apr 29, 2022 at 7:10 PM Wei Xu <weixugc@xxxxxxxxxx> wrote: > > > > > > The current kernel has the basic memory tiering support: Inactive > > > pages on a higher tier NUMA node can be migrated (demoted) to a lower > > > tier NUMA node to make room for new allocations on the higher tier > > > NUMA node. Frequently accessed pages on a lower tier NUMA node can be > > > migrated (promoted) to a higher tier NUMA node to improve the > > > performance. > > > > > > A tiering relationship between NUMA nodes in the form of demotion path > > > is created during the kernel initialization and updated when a NUMA > > > node is hot-added or hot-removed. The current implementation puts all > > > nodes with CPU into the top tier, and then builds the tiering hierarchy > > > tier-by-tier by establishing the per-node demotion targets based on > > > the distances between nodes. > > > > > > The current memory tiering interface needs to be improved to address > > > several important use cases: > > > > > > * The current tiering initialization code always initializes > > > each memory-only NUMA node into a lower tier. But a memory-only > > > NUMA node may have a high performance memory device (e.g. a DRAM > > > device attached via CXL.mem or a DRAM-backed memory-only node on > > > a virtual machine) and should be put into the top tier. > > > > > > * The current tiering hierarchy always puts CPU nodes into the top > > > tier. But on a system with HBM (e.g. GPU memory) devices, these > > > memory-only HBM NUMA nodes should be in the top tier, and DRAM nodes > > > with CPUs are better to be placed into the next lower tier. > > > > > > * Also because the current tiering hierarchy always puts CPU nodes > > > into the top tier, when a CPU is hot-added (or hot-removed) and > > > triggers a memory node from CPU-less into a CPU node (or vice > > > versa), the memory tiering hierarchy gets changed, even though no > > > memory node is added or removed. This can make the tiering > > > hierarchy much less stable. > > > > I'd prefer the firmware builds up tiers topology then passes it to > > kernel so that kernel knows what nodes are in what tiers. No matter > > what nodes are hot-removed/hot-added they always stay in their tiers > > defined by the firmware. I think this is important information like > > numa distances. NUMA distance alone can't satisfy all the usecases > > IMHO. > > Just want to note here that the platform firmware can only describe > the tiers of static memory present at boot. CXL hotplug breaks this > model and the kernel is left to dynamically determine the device's > performance characteristics and the performance of the topology to > reach that device. Now, the platform firmware does set expectations > for the perfomance class of different memory ranges, but there is no > way to know in advance the performance of devices that will be asked > to be physically or logically added to the memory configuration. That > said, it's probably still too early to define ABI for those > exceptional cases where the kernel needs to make a policy decision > about a device that does not fit into the firmware's performance > expectations, but just note that there are limits to the description > that platform firmware can provide. > > I agree that NUMA distance alone is inadequate and the kernel needs to > make better use of data like ACPI HMAT to determine the default > tiering order. Very useful clarification. It should be fine for the kernel to dynamically determine the memory tier of each node. I expect that it can also be fine even if a node gets attached to a different memory device and needs to be assigned into a different tier after another round of hot-remove/hot-add. What can be problematic is that a hot-added node not only changes its own iter, but also causes other existing nodes to change their tiers. This can mess up any tier-based memory accounting. One approach to address this is to: - have tiers being well-defined and stable, e.g. HBM is always in tier-0, direct-attached DRAM and high-performance CXL.mem devices are always in tier-1, slower CXL.mem devices are always in tier-2, and PMEM is always in tier-3. The tier definition is based on the device performance, something similar to the class rating of storage devices (e.g. SD cards). - allow tiers being absent in the system, e.g. a machine may have only tier-1 and tier-3, but have neither tier-0 nor tier-2. - allow demotion to not only the immediate next lower tier, but all lower tiers. The actual selection of demotion order follows the allocation fallback order. This allows tier-1 to directly demote to tier-3 without requiring the presence of tier-2. This approach can ensure that the tiers of existing nodes are stable and permit that the tier of a hot-plugged node is determined dynamically.
