On Fri, 15 Apr 2022 at 12:12, Herbert Xu <herbert@xxxxxxxxxxxxxxxxxxx> wrote: > > On Fri, Apr 15, 2022 at 11:51:49AM +0200, Ard Biesheuvel wrote: > > > > That is the whole point, really: ARCH_DMA_MINALIGN==128 does not mean > > __ctx needs to be aligned to 128 bytes, it only means that it should > > not share a 128 byte cacheline with the preceding fields. So if > > kmalloc() returns buffers that are aligned to whatever alignment the > > platform requires (which will be 64 in most cases), the above > > arrangement ensures that, without requiring that CRYPTO_MINALIGN == > > ARCH_DMA_MINALIGN. > > What if they started sharing a cacheline with the subsequent object? > I guess you could add some more padding at the end though. > Subsequent objects are owned by the driver, and it is the responsibility of the driver not to modify the fields while it is also mapped for DMA (and we have had issues in the past where drivers violated this rule). So as long as ARCH_KMALLOC_ALIGN guarantees actual DMA minimum alignment for both the start and the end, we shouldn't need any explicit padding at the end. > I could accept this as a temporary solution, if you volunteer to > modify all the affected drivers so we can get rid of this bandaid. > I'l do a scan of drivers/crypto to figure out how much we are relying on this to begin with.
