在 2022/4/13 1:08, Robin Murphy 写道:
On 12/04/2022 8:25 am, Tong Tiangen wrote:
[...]
diff --git a/arch/arm64/include/asm/asm-uaccess.h
b/arch/arm64/include/asm/asm-uaccess.h
index 0557af834e03..bb17f0829042 100644
--- a/arch/arm64/include/asm/asm-uaccess.h
+++ b/arch/arm64/include/asm/asm-uaccess.h
@@ -92,4 +92,20 @@ alternative_else_nop_endif
_asm_extable 8888b,\l;
.endm
+
+ .macro user_ldp_mc l, reg1, reg2, addr, post_inc
+8888: ldtr \reg1, [\addr];
+8889: ldtr \reg2, [\addr, #8];
+ add \addr, \addr, \post_inc;
+
+ _asm_extable_uaccess_mc 8888b, \l;
+ _asm_extable_uaccess_mc 8889b, \l;
+ .endm
You're replacing the only user of this, so please just
s/_asm_extable/_asm_extable_uaccess_mc/ in the existing macro and save
the rest of the churn.
Furthermore, how come you're not similarly updating user_stp, given that
you *are* updating the other stores in copy_to_user?
I think all load/store instructions should be handled.
Generally speaking, the load operation will receive a sea when consuming
a hardware memory error, and the store operation will not receive a sea
when consuming a hardware error. Depends on chip behavior.
So add store class instructions to processed is no harm.
If there is any problem with my understanding, correct me.
Thanks,
Tong.
+
+ .macro user_ldst_mc l, inst, reg, addr, post_inc
+8888: \inst \reg, [\addr];
+ add \addr, \addr, \post_inc;
+
+ _asm_extable_uaccess_mc 8888b, \l;
+ .endm
[...]
