On 10/21/21 5:21 AM, Nadav Amit wrote: > The first TLB flush is only necessary to prevent the dirty bit (and with > a lesser importance the access bit) from changing while the PTE is > modified. However, this is not necessary as the x86 CPUs set the > dirty-bit atomically with an additional check that the PTE is (still) > present. One caveat is Intel's Knights Landing that has a bug and does > not do so. First, did I miss the check in this patch for X86_BUG_PTE_LEAK? I don't see it anywhere. > - * pmdp_invalidate() is required to make sure we don't miss > - * dirty/young flags set by hardware. This got me thinking... In here: > https://lore.kernel.org/lkml/20160708001909.FB2443E2@xxxxxxxxxxxxxxxxxx/ I wrote: > These bits are truly "stray". In the case of the Dirty bit, the > thread associated with the stray set was *not* allowed to write to > the page. This means that we do not have to launder the bit(s); we > can simply ignore them. Is the goal of your proposed patch here to ensure that the dirty bit is not set at *all*? Or, is it to ensure that a dirty bit which we need to *launder* is never set?
