tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master head: d3134eb5de8546a214c028fb7195e764b89da7d4 commit: 1a6f854f7daab100ff0a94d31f35a387b462b4d1 [4671/7405] spi: cadence-quadspi: Add Xilinx Versal external DMA support config: sh-allmodconfig (attached as .config) compiler: sh4-linux-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=1a6f854f7daab100ff0a94d31f35a387b462b4d1 git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git git fetch --no-tags linux-next master git checkout 1a6f854f7daab100ff0a94d31f35a387b462b4d1 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=sh If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@xxxxxxxxx> All errors (new ones prefixed by >>): In file included from drivers/spi/spi-cadence-quadspi.c:12: drivers/spi/spi-cadence-quadspi.c: In function 'cqspi_versal_indirect_read_dma': >> drivers/spi/spi-cadence-quadspi.c:950:55: error: implicit conversion from 'enum dma_transfer_direction' to 'enum dma_data_direction' [-Werror=enum-conversion] 950 | dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_DEV_TO_MEM); | ^~~~~~~~~~~~~~ include/linux/dma-mapping.h:407:70: note: in definition of macro 'dma_unmap_single' 407 | #define dma_unmap_single(d, a, s, r) dma_unmap_single_attrs(d, a, s, r, 0) | ^ cc1: all warnings being treated as errors vim +950 drivers/spi/spi-cadence-quadspi.c 835 836 static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, 837 u_char *rxbuf, loff_t from_addr, 838 size_t n_rx) 839 { 840 struct cqspi_st *cqspi = f_pdata->cqspi; 841 struct device *dev = &cqspi->pdev->dev; 842 void __iomem *reg_base = cqspi->iobase; 843 u32 reg, bytes_to_dma; 844 loff_t addr = from_addr; 845 void *buf = rxbuf; 846 dma_addr_t dma_addr; 847 u8 bytes_rem; 848 int ret = 0; 849 850 bytes_rem = n_rx % 4; 851 bytes_to_dma = (n_rx - bytes_rem); 852 853 if (!bytes_to_dma) 854 goto nondmard; 855 856 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); 857 if (ret) 858 return ret; 859 860 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 861 reg |= CQSPI_REG_CONFIG_DMA_MASK; 862 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 863 864 dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE); 865 if (dma_mapping_error(dev, dma_addr)) { 866 dev_err(dev, "dma mapping failed\n"); 867 return -ENOMEM; 868 } 869 870 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 871 writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES); 872 writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL, 873 reg_base + CQSPI_REG_INDTRIG_ADDRRANGE); 874 875 /* Clear all interrupts. */ 876 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 877 878 /* Enable DMA done interrupt */ 879 writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK, 880 reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN); 881 882 /* Default DMA periph configuration */ 883 writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA); 884 885 /* Configure DMA Dst address */ 886 writel(lower_32_bits(dma_addr), 887 reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR); 888 writel(upper_32_bits(dma_addr), 889 reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB); 890 891 /* Configure DMA Src address */ 892 writel(cqspi->trigger_address, reg_base + 893 CQSPI_REG_VERSAL_DMA_SRC_ADDR); 894 895 /* Set DMA destination size */ 896 writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE); 897 898 /* Set DMA destination control */ 899 writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL, 900 reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL); 901 902 writel(CQSPI_REG_INDIRECTRD_START_MASK, 903 reg_base + CQSPI_REG_INDIRECTRD); 904 905 reinit_completion(&cqspi->transfer_complete); 906 907 if (!wait_for_completion_timeout(&cqspi->transfer_complete, 908 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) { 909 ret = -ETIMEDOUT; 910 goto failrd; 911 } 912 913 /* Disable DMA interrupt */ 914 writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 915 916 /* Clear indirect completion status */ 917 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, 918 cqspi->iobase + CQSPI_REG_INDIRECTRD); 919 dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 920 921 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 922 reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 923 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 924 925 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, 926 PM_OSPI_MUX_SEL_LINEAR); 927 if (ret) 928 return ret; 929 930 nondmard: 931 if (bytes_rem) { 932 addr += bytes_to_dma; 933 buf += bytes_to_dma; 934 ret = cqspi_indirect_read_execute(f_pdata, buf, addr, 935 bytes_rem); 936 if (ret) 937 return ret; 938 } 939 940 return 0; 941 942 failrd: 943 /* Disable DMA interrupt */ 944 writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 945 946 /* Cancel the indirect read */ 947 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 948 reg_base + CQSPI_REG_INDIRECTRD); 949 > 950 dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_DEV_TO_MEM); 951 952 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 953 reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 954 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 955 956 zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); 957 958 return ret; 959 } 960 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx
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