On 7/16/21 1:38 PM, Suzuki K Poulose wrote: > On 16/07/2021 08:06, Anshuman Khandual wrote: >> >> On 7/14/21 1:51 PM, Suzuki K Poulose wrote: >>> On 14/07/2021 03:21, Anshuman Khandual wrote: >>>> Detect FEAT_LPA2 implementation early enough during boot when requested via >>>> CONFIG_ARM64_PA_BITS_52_LPA2 and remember in a variable arm64_lpa2_enabled. >>>> This variable could then be used to turn on TCR_EL1.TCR_DS effecting the 52 >>>> bits PA range or fall back to default 48 bits PA range if FEAT_LPA2 feature >>>> was requested but found not to be implemented. >>>> >>>> Signed-off-by: Anshuman Khandual <anshuman.khandual@xxxxxxx> >>>> --- >>>> arch/arm64/include/asm/memory.h | 1 + >>>> arch/arm64/kernel/head.S | 15 +++++++++++++++ >>>> arch/arm64/mm/mmu.c | 3 +++ >>>> arch/arm64/mm/proc.S | 9 +++++++++ >>>> 4 files changed, 28 insertions(+) >>>> >>>> diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h >>>> index 824a365..d0ca002 100644 >>>> --- a/arch/arm64/include/asm/memory.h >>>> +++ b/arch/arm64/include/asm/memory.h >>>> @@ -178,6 +178,7 @@ >>>> #include <asm/bug.h> >>>> extern u64 vabits_actual; >>>> +extern u64 arm64_lpa2_enabled; >>>> extern s64 memstart_addr; >>>> /* PHYS_OFFSET - the physical address of the start of memory. */ >>>> diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S >>>> index 6444147..9cf79ea 100644 >>>> --- a/arch/arm64/kernel/head.S >>>> +++ b/arch/arm64/kernel/head.S >>>> @@ -94,6 +94,21 @@ SYM_CODE_START(primary_entry) >>>> adrp x23, __PHYS_OFFSET >>>> and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0 >>>> bl set_cpu_boot_mode_flag >>>> + >>>> +#ifdef CONFIG_ARM64_PA_BITS_52_LPA2 >>>> + mrs x10, ID_AA64MMFR0_EL1 >>>> + ubfx x10, x10, #ID_AA64MMFR0_TGRAN_SHIFT, 4 >>>> + cmp x10, #ID_AA64MMFR0_TGRAN_LPA2 >>>> + b.ne 1f >>> >>> For the sake of forward compatibility, this should be "b.lt" >> Right, I guess we could assume that the feature will be present from the >> current ID_AA64MMFR0_TGRAN_LPA2 values onward in the future. But should >> not this also be capped at ID_AA64MMFR0_TGRAN_SUPPORTED_MAX as the upper >> limit is different for 4K and 16K page sizes. > > Absolutely. ID_AA64MMFR0_TGRAN_SUPPORTED_MAX check there is not required as __enable_mmu() already performs the required boundary check for a given page size support.
